LM3S1435 Luminary Micro, Inc, LM3S1435 Datasheet - Page 436

• Manufacturer Part Number: LM3S1435
• Description: Lm3s1435 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Reset
Reset
Type
Type
Pulse Width Modulator (PWM)
PWM0 Control (PWM0CTL)
Base 0x4002.8000
Offset 0x040
Type R/W, reset 0x0000.0000
436
Bit/Field
31:6
5
4
3
2
1
RO
RO
31
15
0
0
Register 10: PWM0 Control (PWM0CTL), offset 0x040
This register configures the PWM signal generation block. The Register Update mode, Debug mode,
Counting mode, and Block Enable mode are all controlled via this register. The block produces the
PWM signals, which can be either two independent PWM signals (from the same counter), or a
paired set of PWM signals with dead-band delays added.
The PWM0 block produces the PWM0 and PWM1 outputs.
RO
RO
30
14
0
0
CmpBUpd
CmpAUpd
LoadUpd
reserved
RO
RO
29
13
0
0
Debug
Name
Mode
RO
RO
28
12
0
0
RO
RO
27
11
0
0
reserved
Type
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
26
10
0
0
Reset
0x00
RO
RO
25
0
9
0
0
0
0
0
0
Preliminary
RO
RO
24
0
8
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Comparator B Update Mode
Same as CmpAUpd but for the comparator B register.
Comparator A Update Mode
The Update mode for the comparator A register. When not set, updates
to the register are reflected to the comparator the next time the counter
is 0. When set, updates to the register are delayed until the next time
the counter is 0 after a synchronous update has been requested through
the PWM Master Control (PWMCTL) register (see page 427).
Load Register Update Mode
The Update mode for the load register. When not set, updates to the
register are reflected to the counter the next time the counter is 0. When
set, updates to the register are delayed until the next time the counter
is 0 after a synchronous update has been requested through the PWM
Master Control (PWMCTL) register.
Debug Mode
The behavior of the counter in Debug mode. When not set, the counter
stops running when it next reaches 0, and continues running again when
no longer in Debug mode. When set, the counter always runs.
Counter Mode
The mode for the counter. When not set, the counter counts down from
the load value to 0 and then wraps back to the load value (Count-Down
mode). When set, the counter counts up from 0 to the load value, back
down to 0, and then repeats (Count-Up/Down mode).
reserved
RO
RO
23
0
7
0
RO
RO
22
0
6
0
CmpBUpd
R/W
RO
21
0
5
0
CmpAUpd
R/W
RO
20
0
4
0
LoadUpd
R/W
RO
19
0
3
0
Debug
R/W
RO
18
0
2
0
July 25, 2008
Mode
R/W
RO
17
0
1
0
Enable
R/W
RO
16
0
0
0