LM3S818 Luminary Micro, Inc, LM3S818 Datasheet - Page 338

• Manufacturer Part Number: LM3S818
• Description: Lm3s818 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Pulse Width Modulator (PWM)
338
Reset
Reset
Type
Type
Bit/Field
31:12
11:10
PWMn Generator A Control (PWMnGENA)
9:8
7:6
5:4
RO
RO
31
15
0
0
Register 34: PWM0 Generator A Control (PWM0GENA), offset 0x060
Register 35: PWM1 Generator A Control (PWM1GENA), offset 0x0A0
Register 36: PWM2 Generator A Control (PWM2GENA), offset 0x0E0
These registers control the generation of the PWMNA signal based on the load and zero output
pulses from the counter, as well as the compare A and compare B pulses from the comparators
(PWM0GENA controls the PWM generator 0 block, and so on). When the counter is running in
Count-Down mode, only four of these events occur; when running in Count-Up/Down mode, all six
occur. These events provide great flexibility in the positioning and duty cycle of the PWM signal
that is produced.
The PWM0GENA register controls generation of the PWM0A signal; PWM1GENA, the PWM1A
signal; and PWM2GENA, the PWM2A signal.
Each field in these registers can take on one of the values defined in Table 15-2, which defines the
effect of the event on the output signal.
If a zero or load event coincides with a compare A or compare B event, the zero or load action is
taken and the compare A or compare B action is ignored. If a compare A event coincides with a
compare B event, the compare A action is taken and the compare B action is ignored.
RO
RO
30
14
0
0
reserved
ActCmpBD
ActCmpBU
ActCmpAD
ActCmpAU
reserved
Name
RO
RO
29
13
0
0
RO
RO
28
12
0
0
Type
R/W
R/W
R/W
R/W
R/W
RO
RO
27
11
ActCmpBD
0
0
R/W
RO
26
10
0
0
Reset
R/W
RO
25
ActCmpBU
0
9
0
0
0
0
0
0
Preliminary
R/W
RO
24
0
8
0
reserved
Description
Reserved bits return an indeterminate value, and should
never be changed.
The action to be taken when the counter matches
comparator B while counting down.
The action to be taken when the counter matches
comparator B while counting up. Occurs only when the
Mode bit in the PWMnCTL register (see page 328) is set
to 1.
The action to be taken when the counter matches
comparator A while counting down.
The action to be taken when the counter matches
comparator A while counting up.Occurs only when the
Mode bit in the PWMnCTL register is set to 1.
R/W
RO
23
ActCmpAD
0
7
0
R/W
RO
22
0
6
0
R/W
RO
21
ActCmpAU
0
5
0
R/W
RO
20
0
4
0
R/W
RO
19
0
3
0
ActLoad
R/W
RO
18
0
2
0
February 6, 2007
R/W
RO
17
0
1
0
ActZero
R/W
RO
16
0
0
0