LM3S2965 Luminary Micro, Inc, LM3S2965 Datasheet - Page 16

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LM3S2965

Manufacturer Part Number
LM3S2965
Description
Lm3s2965 Arm Microcontroller
Manufacturer
Luminary Micro, Inc
Datasheet

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Table of Contents
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
Register 26:
Register 27:
Universal Asynchronous Receivers/Transmitters (UARTs) ..................................................... 305
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
16
ADC Underflow Status (ADCUSTAT), offset 0x018 ........................................................... 288
ADC Sample Sequencer Priority (ADCSSPRI), offset 0x020 ............................................. 289
ADC Processor Sample Sequence Initiate (ADCPSSI), offset 0x028 ................................. 290
ADC Sample Averaging Control (ADCSAC), offset 0x030 ................................................. 291
ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0), offset 0x040 ............... 292
ADC Sample Sequence Control 0 (ADCSSCTL0), offset 0x044 ........................................ 294
ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0), offset 0x048 ................................ 297
ADC Sample Sequence Result FIFO 1 (ADCSSFIFO1), offset 0x068 ................................ 297
ADC Sample Sequence Result FIFO 2 (ADCSSFIFO2), offset 0x088 ................................ 297
ADC Sample Sequence Result FIFO 3 (ADCSSFIFO3), offset 0x0A8 ............................... 297
ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0), offset 0x04C ............................. 298
ADC Sample Sequence FIFO 1 Status (ADCSSFSTAT1), offset 0x06C ............................. 298
ADC Sample Sequence FIFO 2 Status (ADCSSFSTAT2), offset 0x08C ............................ 298
ADC Sample Sequence FIFO 3 Status (ADCSSFSTAT3), offset 0x0AC ............................ 298
ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1), offset 0x060 ............... 299
ADC Sample Sequence Input Multiplexer Select 2 (ADCSSMUX2), offset 0x080 ............... 299
ADC Sample Sequence Control 1 (ADCSSCTL1), offset 0x064 ........................................ 300
ADC Sample Sequence Control 2 (ADCSSCTL2), offset 0x084 ........................................ 300
ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3), offset 0x0A0 ............... 302
ADC Sample Sequence Control 3 (ADCSSCTL3), offset 0x0A4 ........................................ 303
ADC Test Mode Loopback (ADCTMLB), offset 0x100 ....................................................... 304
UART Data (UARTDR), offset 0x000 ............................................................................... 313
UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 ........................... 315
UART Flag (UARTFR), offset 0x018 ................................................................................ 317
UART IrDA Low-Power Register (UARTILPR), offset 0x020 ............................................. 319
UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ............................................ 320
UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ....................................... 321
UART Line Control (UARTLCRH), offset 0x02C ............................................................... 322
UART Control (UARTCTL), offset 0x030 ......................................................................... 324
UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ........................................... 326
UART Interrupt Mask (UARTIM), offset 0x038 ................................................................. 328
UART Raw Interrupt Status (UARTRIS), offset 0x03C ...................................................... 330
UART Masked Interrupt Status (UARTMIS), offset 0x040 ................................................. 331
UART Interrupt Clear (UARTICR), offset 0x044 ............................................................... 332
UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ..................................... 334
UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ..................................... 335
UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ..................................... 336
UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ..................................... 337
UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ...................................... 338
UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ...................................... 339
UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ...................................... 340
UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ..................................... 341
UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................ 342
UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ........................................ 343
UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ........................................ 344
UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................ 345
Preliminary
July 25, 2008

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