LM3S2965 Luminary Micro, Inc, LM3S2965 Datasheet - Page 17

• Manufacturer Part Number: LM3S2965
• Description: Lm3s2965 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Synchronous Serial Interface (SSI) ............................................................................................ 346
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Inter-Integrated Circuit (I
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Controller Area Network (CAN) Module ..................................................................................... 418
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July 25, 2008
SSI Control 0 (SSICR0), offset 0x000 .............................................................................. 358
SSI Control 1 (SSICR1), offset 0x004 .............................................................................. 360
SSI Data (SSIDR), offset 0x008 ...................................................................................... 362
SSI Status (SSISR), offset 0x00C ................................................................................... 363
SSI Clock Prescale (SSICPSR), offset 0x010 .................................................................. 365
SSI Interrupt Mask (SSIIM), offset 0x014 ......................................................................... 366
SSI Raw Interrupt Status (SSIRIS), offset 0x018 .............................................................. 368
SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................ 369
SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... 370
SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................. 371
SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ............................................. 372
SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ............................................. 373
SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................ 374
SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................. 375
SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ............................................. 376
SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ............................................. 377
SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................ 378
SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ............................................... 379
SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ............................................... 380
SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ............................................... 381
SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ............................................... 382
I
I
I
I
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I
I
I
I
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I
CAN Control (CANCTL), offset 0x000 ............................................................................. 431
CAN Status (CANSTS), offset 0x004 ............................................................................... 433
CAN Error Counter (CANERR), offset 0x008 ................................................................... 436
CAN Bit Timing (CANBIT), offset 0x00C .......................................................................... 437
CAN Interrupt (CANINT), offset 0x010 ............................................................................. 439
CAN Test (CANTST), offset 0x014 .................................................................................. 440
CAN Baud Rate Prescalar Extension (CANBRPE), offset 0x018 ....................................... 442
2
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C Master Slave Address (I2CMSA), offset 0x000 ........................................................... 397
C Master Control/Status (I2CMCS), offset 0x004 ........................................................... 398
C Master Data (I2CMDR), offset 0x008 ......................................................................... 402
C Master Timer Period (I2CMTPR), offset 0x00C ........................................................... 403
C Master Interrupt Mask (I2CMIMR), offset 0x010 ......................................................... 404
C Master Raw Interrupt Status (I2CMRIS), offset 0x014 ................................................. 405
C Master Masked Interrupt Status (I2CMMIS), offset 0x018 ........................................... 406
C Master Interrupt Clear (I2CMICR), offset 0x01C ......................................................... 407
C Master Configuration (I2CMCR), offset 0x020 ............................................................ 408
C Slave Own Address (I2CSOAR), offset 0x000 ............................................................ 410
C Slave Control/Status (I2CSCSR), offset 0x004 ........................................................... 411
C Slave Data (I2CSDR), offset 0x008 ........................................................................... 413
C Slave Interrupt Mask (I2CSIMR), offset 0x00C ........................................................... 414
C Slave Raw Interrupt Status (I2CSRIS), offset 0x010 ................................................... 415
C Slave Masked Interrupt Status (I2CSMIS), offset 0x014 .............................................. 416
C Slave Interrupt Clear (I2CSICR), offset 0x018 ............................................................ 417
2
C) Interface ........................................................................................ 383
Preliminary
LM3S2965 Microcontroller
17