LM3509SDX National Semiconductor Corporation, LM3509SDX Datasheet - Page 14

• Manufacturer Part Number: LM3509SDX
• Description: High Efficiency Boost For White Led S And/or Oled Displays With Dual Current Sinks And I2c Compatible Brightness Control
• Manufacturer: National Semiconductor Corporation

www.national.com
I
The LM3509 is controlled via an I
START and STOP conditions classify the beginning and the
end of the I
transitioning from HIGH to LOW while SCL is HIGH. A STOP
condition is defined as SDA transitioning from LOW to HIGH
while SCL is HIGH. The I
and STOP conditions. The I
I
The chip address for the LM3509 is 0110110 (36h). After the
START condition, the I
followed by a read or write bit (R/W). R/W= 0 indicates a
TRANSFERRING DATA
Every byte on the SDA line must be eight bits long, with the
most significant bit (MSB) transferred first. Each byte of data
must be followed by an acknowledge bit (ACK). The acknowl-
edge related clock pulse (9th clock pulse) is generated by the
master. The master releases SDA (HIGH) during the 9th clock
2
2
C COMPATIBLE INTERFACE
C COMPATIBLE ADDRESS
2
C session. A START condition is defined as SDA
2
C master sends the 7-bit chip address
2
C master always generates START
2
C bus is considered busy after a
2
C compatible interface.
FIGURE 5. Write Sequence to the LM3509
FIGURE 3. Start and Stop Sequences
FIGURE 4. Chip Address
14
START condition and free after a STOP condition. During da-
ta transmission, the I
START conditions. A START and a repeated START condi-
tions are equivalent function-wise. The data on SDA must be
stable during the HIGH period of the clock signal (SCL). In
other words, the state of SDA can only be changed when SCL
is LOW.
WRITE and R/W = 1 indicates a READ. The second byte fol-
lowing the chip address selects the register address to which
the data will be written. The third byte contains the data for
the selected register.
pulse. The LM3509 pulls down SDA during the 9th clock
pulse, signifying an acknowledge. An acknowledge is gener-
ated after each byte has been received. Figure 5 is an exam-
ple of a write sequence to the General Purpose register of the
LM3509.
2
C master can generate repeated
30004337
30004338
30004339