IDT72V285L10PFG IDT, Integrated Device Technology Inc, IDT72V285L10PFG Datasheet - Page 22
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IDT72V285L10PFG
Manufacturer Part Number
IDT72V285L10PFG
Description
IC FIFO SS 65536X18 10NS 64-TQFP
Manufacturer
IDT, Integrated Device Technology Inc
Series
72Vr
Datasheet
1.IDT72V275L15TF8.pdf
(25 pages)
Specifications of IDT72V285L10PFG
Function
Asynchronous
Memory Size
1.1M (65K x 18)
Data Rate
100MHz
Access Time
10ns
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
64-TQFP, 64-VQFP
Configuration
Dual
Density
1.125Mb
Access Time (max)
6.5ns
Word Size
18b
Organization
64Kx18
Sync/async
Synchronous
Expandable
Yes
Bus Direction
Uni-Directional
Package Type
TQFP
Clock Freq (max)
100MHz
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Supply Current
60mA
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
64
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
72V285L10PFG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IDT72V285L10PFG
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Company:
Part Number:
IDT72V285L10PFG8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
NOTES:
1. For IDT Standard mode: D = maximum FIFO depth. D = 32,768 for the IDT72V275 and 65,536 for the IDT72V285.
2. For FWFT mode: D = maximum FIFO depth. D = 32,769 for the IDT72V275 and 65,537 for the IDT72V285.
WCLK
WCLK
NOTES:
1. n = PAE offset.
2. For IDT Standard mode
3. For FWFT mode.
4. t
5. PAE is asserted and updated on the rising edge of WCLK only.
RCLK
RCLK
IDT72V275/72V285 3.3V CMOS SUPERSYNC FIFO
32,768 x 18 and 65,536 x 18
WEN
WEN
REN
REN
PAE
WCLK and the rising edge of RCLK is less than t
SKEW2
HF
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that PAE will go HIGH (after one RCLK cycle plus t
t
CLKH
t
ENS
n words in FIFO
n+1 words in FIFO
Figure 17. Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
t
CLKL
t
ENH
[
(2)
t
D-1
SKEW2
1
2
,
(3)
D/2 words in FIFO
Figure 18. Half-Full Flag Timing (IDT Standard and FWFT Modes)
SKEW2
+ 1
(4)
]
, then the PAE deassertion may be delayed one extra RCLK cycle.
words in FIFO
t
t
PAE
CLKH
TM
(1)
2
,
(2)
t
ENS
t
CLKL
22
t
t
ENH
ENS
t
HF
n+1 words in FIFO
n+2 words in FIFO
t
ENS
[
D-1
D/2 + 1 words in FIFO
t
2
ENH
+ 2
]
(2)
(3)
words in FIFO
,
t
HF
1
(1)
,
(2)
COMMERCIAL AND INDUSTRIAL
PAE
). If the time between the rising edge of
t
PAE
[
D-1
2
TEMPERATURE RANGES
D/2 words in FIFO
2
+ 1
]
words in FIFO
n words in FIFO
n+1 words in FIFO
4512 drw 21
4512 drw 20
(1)
,
(2)
(2)
,
(3)