IDT72V285L10PFG IDT, Integrated Device Technology Inc, IDT72V285L10PFG Datasheet - Page 9
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IDT72V285L10PFG
Manufacturer Part Number
IDT72V285L10PFG
Description
IC FIFO SS 65536X18 10NS 64-TQFP
Manufacturer
IDT, Integrated Device Technology Inc
Series
72Vr
Datasheet
1.IDT72V275L15TF8.pdf
(25 pages)
Specifications of IDT72V285L10PFG
Function
Asynchronous
Memory Size
1.1M (65K x 18)
Data Rate
100MHz
Access Time
10ns
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
64-TQFP, 64-VQFP
Configuration
Dual
Density
1.125Mb
Access Time (max)
6.5ns
Word Size
18b
Organization
64Kx18
Sync/async
Synchronous
Expandable
Yes
Bus Direction
Uni-Directional
Package Type
TQFP
Clock Freq (max)
100MHz
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Supply Current
60mA
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
64
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
72V285L10PFG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IDT72V285L10PFG
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Company:
Part Number:
IDT72V285L10PFG8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
NOTES:
1. The programming method can only be selected at Master Reset.
2. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected.
3. The programming sequence applies to both IDT Standard and FWFT modes.
17
17
IDT72V275/72V285 3.3V CMOS SUPERSYNC FIFO
32,768 x 18 and 65,536 x 18
15
15
14
14
72V275 (32,768 x 18 _ BIT)
LD
0
0
0
X
1
1
1
EMPTY OFFSET REGISTER
03FFH if LD is HIGH at Master Reset
FULL OFFSET REGISTER
03FFH if LD is HIGH at Master Reset
007FH if LD is LOW at Master Reset,
007FH if LD is LOW at Master Reset,
WEN
DEFAULT VALUE
DEFAULT VALUE
X
0
1
1
1
0
1
REN
X
1
0
1
1
0
1
Figure 4. Programmable Flag Offset Programming Sequence
SEN
Figure 3. Offset Register Location and Default Values
1
1
X
X
X
1
0
TM
WCLK
X
X
X
X
0
0
RCLK
9
X
X
X
X
X
17
17
Parallel write to registers:
Empty Offset
Full Offset
Parallel read from registers:
Empty Offset
Full Offset
Serial shift into registers:
30 bits for the 72V275
32 bits for the 72V285
1 bit for each rising WCLK edge
Starting with Empty Offset (LSB)
Ending with Full Offset (MSB)
No Operation
Write Memory
Read Memory
No Operation
16
16
15
15
72V285 (65,536 x 18 _ BIT)
03FFH if LD is HIGH at Master Reset
007FH if LD is LOW at Master Reset,
03FFH if LD is HIGH at Master Reset
007FH if LD is LOW at Master Reset,
EMPTY OFFSET REGISTER
FULL OFFSET REGISTER
72V275
72V285
DEFAULT VALUE
DEFAULT VALUE
COMMERCIAL AND INDUSTRIAL
4512 drw 07
TEMPERATURE RANGES
4512 drw 06
0
0