MT16LSDT12864AG-133B1 Micron, MT16LSDT12864AG-133B1 Datasheet - Page 17

• Manufacturer Part Number: MT16LSDT12864AG-133B1
• Description: DRAM Module, 512MB/1GB (x64), 168-PIN SDRAM DIMM
• Manufacturer: Micron

Notes
64,128 Meg x 64 SDRAM DIMMs
SD8_16C64_128x64AG_A.fm - Rev. A 11/02 EN
10.
11. AC timing and I
12. Other input signals are allowed to transition no
13. I
14. Timing actually specified by
15. Timing actually specified by
3. I
7. AC characteristics assume
8. In addition to meeting the transition rate specifi-
1. All voltages referenced to V
2. This parameter is sampled. V
4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to
6. An initial pause of 100µs is required after power-
9. Outputs measured at 1.5V with equivalent load:
T
MHz.
rates. Specified values are obtained with mini-
mum cycle time and the outputs open.
indicate cycle time at which proper operation
over the full temperature range is ensured.
up, followed by two AUTO REFRESH commands,
before proper device operation is ensured. (V
and V
V
AUTO REFRESH command wake-ups should be
repeated any time the
exceeded.
cation, the clock and CKE must transit between
V
tonic manner.
t
the open circuit condition; it is not a reference to
V
t
with timing referenced to 1.5V crossover point. If
the input transition time is longer than 1ns, then
the timing is referenced at V
(MIN) and no longer at the 1.5V crossover point.
more than once every two clocks and are other-
wise at valid V
properly initialized.
fied as a reference only at minimum cycle rate.
specified as a reference only at minimum cycle
rate.
HZ defines the time at which the output achieves
OH before going High-Z.
DD
DD
A
OH
SS
IH
= 25°C; pin under test biased at 1.4V; f = 1
and V
and V
is dependent on output loading and cycle
specifications are tested after the device is
or V
DDQ
OL
SSQ
IL
. The last valid data element will meet
must be powered up simultaneously.
(or between V
must be at same potential.) The two
IH
Q
DD
or V
tests have V
IL
t
levels.
REF refresh requirement is
t
IL
SS
T = 1ns.
t
.
and V
WR plus
t
50pF
CKS; clock(s) speci-
IL
DD
IL
= 0V and V
, V
(MAX) and V
IH
DDQ
) in a mono-
t
RP; clock(s)
= +3.3V;
IH
= 3V
DD
IH
17
16. Timing actually specified by
17. Required clocks are specified by JEDEC function-
18. The I
19. Address transitions average one transition every
20. CLK must be toggled a minimum of two times
21. Based on
22. V
23. The clock frequency must remain constant (stable
24. Auto precharge mode only. The precharge timing
25. Precharge mode only.
26. JEDEC and PC100 specify three clocks.
27.
28. Parameter guaranteed by design.
29. For -13E, CL = 2 and
30. CKE is HIGH during refresh command period
31. Refer to device data sheet for timing waveforms.
32. The value of
33. Leakage number reflects the worst case leakage
ality and are not dependent on any timing param-
eter.
tionally according to the amount of frequency
alteration for the test condition.
two clocks.
during this period.
133 and -13E.
width £ 3ns, and the pulse width cannot be
greater than one third of the cycle rate. V
shoot: V
clock is defined as a signal cycling within timing
constraints specified for the clock pin) during
access or precharge states (READ, WRITE, includ-
ing
be used to reduce the data rate.
budget (
and 7ns for -10E after the first clock delay, after
the last WRITE is executed. May not exceed limit
set for precharge mode.
t
and is guaranteed by design.
and
t
actually a nominal value and does not result in a
fail value.
ules is calculated from
possible through the module pin, not what each
memory device contributes.
AC for -133/-13E at CL = 3 with no load is 4.6ns
RFC (MIN) else CKE is LOW. The I
Micron Technology, Inc., reserves the right to change products or specifications without notice.
IH
t
overshoot: V
WR, and PRECHARGE commands). CKE may
t
CK = 7.5ns; for -10E, CL=2 and
DD
IL
current will increase or decrease propor-
t
RP) begins 7ns for -13E; 7.5ns for -133
t
168-PIN SDRAM DIMMs
CK = 10ns for -10E, and
(MIN) = -2V for a pulse width £ 3ns.
t
RAS used in -13E speed grade mod-
IH
512MB / 1GB (x64)
(MAX) = V
t
CK = 7.5ns; for -133, CL = 3
t
RC -
t
t
RP .
WR.
DDQ
©2002, Micron Technology Inc.
t
+ 2V for a pulse
CK = 7.5ns for -
t
CK = 10ns
ADVANCE
DD
6 limit is
IL
under-