MT16LSDT6464 Micron, MT16LSDT6464 Datasheet - Page 19

• Manufacturer Part Number: MT16LSDT6464
• Description: 168-Pin SDRAM DIMMs (x64)
• Manufacturer: Micron

SERIAL PRESENCE-DETECT EEPROM DC OPERATING CONDITIONS
(Notes: 1) (V
SERIAL PRESENCE-DETECT EEPROM AC OPERATING CONDITIONS
(Note: 1) (V
NOTE: 1. All voltages referenced to V
32, 64 Meg x 64 SDRAM DIMMs
SD8_16C32_64x64AG_B.p65–Rev. B, Pub. 8/01
PARAMETER/CONDITION
SUPPLY VOLTAGE
INPUT HIGH VOLTAGE: Logic 1; All inputs
INPUT LOW VOLTAGE: Logic 0; All inputs
OUTPUT LOW VOLTAGE: I
INPUT LEAKAGE CURRENT: V
OUTPUT LEAKAGE CURRENT: V
STANDBY CURRENT:
SCL = SDA = V
POWER SUPPLY CURRENT:
SCL clock frequency = 100 KHz
PARAMETER/CONDITION
SCL LOW to SDA data-out valid
Time the bus must be free before a new transition can start
Data-out hold time
SDA and SCL fall time
Data-in hold time
Start condition hold time
Clock HIGH period
Noise suppression time constant at SCL, SDA inputs
Clock LOW period
SDA and SCL rise time
SCL clock frequency
Data-in setup time
Start condition setup time
Stop condition setup time
WRITE cycle time
2. The SPD EEPROM WRITE cycle time (
EEPROM internal erase/program cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA
remains HIGH due to pull-up resistor, and the EEPROM does not respond to its slave address.
DD
DD
= +3.3V ±0.3V)
= +3.3V ±0.3V)
DD
- 0.3V; All other inputs = GND or 3.3V +10%
OUT
IN
= 3mA
= GND to V
OUT
SS
.
= GND to V
t
WRC) is the time from a valid stop condition of a write sequence to the end of the
DD
DD
19
SYMBOL
t
t
t
t
t
HD:DAT
168-PIN SDRAM DIMMs
HD:STA
SU:DAT
SU:STO
SU:STA
t
t
t
t
HIGH
LOW
t
WRC
t
t
BUF
SCL
AA
DH
t
t
SYMBOL
t
R
F
I
256MB / 512MB (x64)
V
V
V
V
I
I
I
I
LO
CC
SB
DD
OL
LI
IH
IL
MIN
300
250
0.3
4.7
4.7
4.7
4.7
0
4
4
V
DD
MIN
-1
3
–
–
–
–
–
x 0.7 V
MAX
300
100
100
3.5
10
1
V
DD
DD
MAX
©2001, Micron Technology, Inc.
UNITS
3.6
0.4
10
10
30
KHz
2
ms
+ 0.5
x 0.3
µs
µs
ns
ns
µs
µs
µs
ns
µs
µs
ns
µs
µs
UNITS
NOTES
mA
µA
µA
µA
V
V
V
V
2