MT18LSDT12872AG-133 Micron, MT18LSDT12872AG-133 Datasheet - Page 24

• Manufacturer Part Number: MT18LSDT12872AG-133
• Description: 1GB SDRAM UDIMM
• Manufacturer: Micron

Table 21:
PDF: 09005aef8088b1bf/Source: 09005aef808807ca
SD9_18C64_128X72AG.fm - Rev. C 6/05 EN
Parameter/Condition
Stop condition setup time
WRITE cycle time
Serial Presence-Detect EEPROM AC Operating Conditions (continued)
All voltages referenced to V
Notes: 1. To avoid spurious start and stop conditions, a minimum delay is placed between SCL = 1
2. This parameter is sampled.
3. For a restart condition or following a WRITE cycle.
4. The SPD EEPROM WRITE cycle time (
and the falling or rising edge of SDA.
write sequence to the end of the EEPROM internal ERASE/PROGRAM cycle. During the
WRITE cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-
up resistor, and the EEPROM does not respond to its slave address.
SS
512MB (SR), 1GB (DR): (x72, ECC) 168-Pin SDRAM UDIMM
; V
DDSPD
= +2.3V to +3.6V
24
Symbol
t
SU:STO
t
WRC
t
WRC) is the time from a valid stop condition of a
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Min
0.6
Serial Presence Detect
Max
10
©2002 Micron Technology, Inc. All rights reserved.
Units
ms
µs
Notes
4