MT18LSDT12872AG-133 Micron, MT18LSDT12872AG-133 Datasheet - Page 8

• Manufacturer Part Number: MT18LSDT12872AG-133
• Description: 1GB SDRAM UDIMM
• Manufacturer: Micron

General Description
Serial Presence-Detect Operation
Initialization
PDF: 09005aef8088b1bf/Source: 09005aef808807ca
SD9_18C64_128X72AG.fm - Rev. C 6/05 EN
The MT9LSDT6472A and MT18LSDT12872A modules are high-speed CMOS, dynamic
random-access, 512MB and 1GB DIMMs organized in a x72 configuration. These mod-
ules use internally configured quad-bank SDRAMs with a synchronous interface (all sig-
nals are registered on the positive edge of the clock signal CK).
Read and write accesses to these SDRAM modules are burst oriented; accesses start at a
selected location and continue for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVE command, which is then
followed by a READ or WRITE command. The address bits registered coincident with the
ACTIVE command are used to select the device bank and row to be accessed (BA0, BA1
select the device bank, A0–A12 select the device row). The address bits registered coinci-
dent with the READ or WRITE command are used to select the starting column location
for the burst access.
These modules provide for programmable READ or WRITE burst lengths of 1, 2, 4, or 8
locations, or the full page, with a burst terminate option. An AUTO PRECHARGE func-
tion may be enabled to provide a self-timed row precharge that is initiated at the end of
the burst sequence.
These modules use an internal pipelined architecture to achieve high-speed operation.
This architecture is compatible with the 2n rule of prefetch architectures, but it also
allows the column address to be changed on every clock cycle to achieve a high-speed,
fully random access. Precharging one device bank while accessing one of the other three
device banks will hide the precharge cycles and provide seamless, high-speed, random-
access operation.
The modules are designed to operate in 3.3V, low-power memory systems. An auto
refresh mode is provided, along with a power-saving, power-down mode. All inputs and
outputs are LVTTL-compatible.
SDRAM modules offer substantial advances in DRAM operating performance, including
the ability to synchronously burst data at a high data rate with automatic column-
address generation, the ability to interleave between internal device banks in order to
hide precharge time and the capability to randomly change column addresses on each
clock cycle during a burst access. For more information regarding SDRAM operation,
refer to the 512Mb SDRAM component data sheet.
These modules incorporate serial presence-detect (SPD). The SPD function is imple-
mented using a 2,048-bit EEPROM. This nonvolatile storage device contains 256 bytes.
The first 128 bytes can be programmed by Micron to identify the module type and vari-
ous SDRAM organizations and timing parameters. The remaining 128 bytes of storage
are available for use by the customer. System READ/WRITE operations between the
master (system logic) and the slave EEPROM device (DIMM) occur via a standard I
bus using the DIMM’s SCL (clock) and SDA (data) signals, together with SA (2:0), which
provide 8 unique DIMM/EEPROM addresses.
SDRAMs must be powered up and initialized in a predefined manner. Operational pro-
cedures other than those specified may result in undefined operation. Once power is
applied to V
defined as a signal cycling within timing constraints specified for the clock pin), the
SDRAM requires a 100µs delay prior to issuing any command other than a COMMAND
DD
512MB (SR), 1GB (DR): (x72, ECC) 168-Pin SDRAM UDIMM
and V
DD
Q (simultaneously) and the clock is stable (stable clock is
8
Micron Technology, Inc., reserves the right to change products or specifications without notice.
General Description
©2002 Micron Technology, Inc. All rights reserved.
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C