MT18VDDT12872PHG-265 Micron, MT18VDDT12872PHG-265 Datasheet - Page 17

• Manufacturer Part Number: MT18VDDT12872PHG-265
• Description: 1GB DDR SDRAM SODIMM
• Manufacturer: Micron

pdf: 09005aef81697898/source: 09005aef8169786e
DD18C128x72PHG.fm - Rev. A 10/04 EN
22. The valid data window is derived by achieving
23. Each byte lane has a corresponding DQS.
24. This limit is actually a nominal value and does not
25. To maintain a valid level, the transitioning edge of
the DRAM controller greater than eight refresh
cycles is not allowed.
other specifications:
(
directly porportional with the clock duty cycle
and a practical data valid window can be derived.
The clock is allowed a maximum duty cycle varia-
tion of 45/55, beyon which functionality is uncer-
tain. Figure 7, Derating Data Valid Window, shows
derating curves for duty cycles ranging between
50/50 and 45/55.
result in a fail value. CKE is HIGH during
REFRESH command period (
CKE is LOW (i.e., during standby).
the input must:
a. Sustain a constant slew rate from the current
3.8
3.6
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
1.8
t
QH =
AC level through to the target AC level, V
or V
50/50
t
IH
HP -
3.750
2.500
(
AC
t
).
N/A
QHS). The data valid window derates
49.5/50.5
3.700
-26A/-265 @
-262/-26A/-265 @
-335 @
2.463
t
HP (
t
CK = 6ns
t
49/51
Figure 7: Derating Data Valid Window
3.650
t
CK/2),
CK = 10ns
2.425
t
CK = 7.5ns
t
RFC [MIN]) else
t
DQSQ, and
48.5/52.5
3.600
2.388
IL
3.550
48/52
t
(
QH
AC
2.350
)
Clock Duty Cycle
17
47.5/53.5
3.500
26. JEDEC specifies CK and CK# input slew rate must
27. DQ and DM input slew rates must not deviate
28. V
29. The clock is allowed up to ±150ps of jitter. Each
30. READs and WRITEs with auto precharge are not
2.313
b. Reach at least the target AC level.
c. After the AC target level is reached, continue to
200-PIN DDR SDRAM SODIMM
be 1V/ns (2V/ns differentially).
from DQS by more than 10 percent. If the DQ/
DM/DQS slew rate is less than 0.5V/ns, timing
must be derated: 50ps must be added to
t
slew rate exceeds 4V/ns, functionality is uncer-
tain.
not active while any bank is active.
timing parameter is allowed to vary by the same
amount.
allowed to be issued until
fied prior to the internal precharge command
being issued.
DH for each 100mv/ns reduction in slew rate. If
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD
maintain at least the target DC level, V
V
IH
3.450
47/53
must not vary more than 4 percent if CKE is
(
2.275
DC
).
46.5/54.5
3.400
2.238
1GB (x72, ECC, PLL)
3.350
46/54
©2004 Micron Technology, Inc. All rights reserved.
2.200
t
RAS (MIN) can be satis-
45.5/55.5
3.300
2.163
IL
t
3.250
45/55
DS and
(
DC
2.125
) or