MT18VDDT12872PHG-265 Micron, MT18VDDT12872PHG-265 Datasheet - Page 21

• Manufacturer Part Number: MT18VDDT12872PHG-265
• Description: 1GB DDR SDRAM SODIMM
• Manufacturer: Micron

Table 15: PLL Clock Driver Timing Requirements and Switching Characteristics
Note: 1
NOTE:
pdf: 09005aef81697898/source: 09005aef8169786e
DD18C128x72PHG.fm - Rev. A 10/04 EN
PARAMETER
Operating Clock Frequency
Input Duty Cycle
Stabilization Time
Cycle to Cycle Jitter
Static Phase Offset
Output Clock Skew
Period Jitter
Half-Period Jitter
Input Clock Slew Rate
Output Clock Slew Rate
1. The timing and switching specifications for the PLL listed above are critical for proper operation of the DDR SDRAM
2. The PLL must be able to handle spread spectrum induced skew.
3. Operating clock frequency indicates a range over which the PLL must be able to lock, but in which it is not required
4. Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its
5. Static Phase Offset does not include Jitter.
6. Period Jitter and Half-Period Jitter specifications are separate specifications that must be met independently of each
7. The Output Slew Rate is determined from the IBIS model:
Registered DIMMs. These are meant to be a subset of the parameters for the specific device used on the module.
Detailed information for this PLL is available in JEDEC Standard JESD82.
to meet the other timing parameters. (Used for low-speed system debug.)
reference signal after power up.
other.
SYMBOL
t
t
t
JIT
t
STAB
JIT
t
t
t
JIT
f
t
SK
t
LS
DC
CK
LS
HPER
PER
CC
O
O
I
MIN
-100
-75
-50
-75
1.0
1.0
60
40
-
-
V
21
DD
0ºC
NOMINAL
CDCV857
= 2.5V ± 0.2V
GND
V
DD
0
-
-
-
-
-
-
-
-
-
T
A
200-PIN DDR SDRAM SODIMM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
70ºC
V
V
CK
CK
R=60
R=60
MAX
170
100
100
100
60
75
50
75
4
2
V
DD
1GB (x72, ECC, PLL)
/2
©2004 Micron Technology, Inc. All rights reserved.
UNITS
MHz
V/ns
V/ns
ms
%
ps
ps
ps
ps
ps
NOTES
2, 3
4
5
6
6
7