IDT72V295L15PF IDT, Integrated Device Technology Inc, IDT72V295L15PF Datasheet
IDT72V295L15PF
Specifications of IDT72V295L15PF
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IDT72V295L15PF Summary of contents
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FEATURES: • Choose among the following memory organizations: ⎯ ⎯ ⎯ ⎯ ⎯ IDT72V295 131,072 x 18 IDT72V2105 ⎯ ⎯ ⎯ ⎯ ⎯ 262,144 x 18 • Pin-compatible with the IDT72V255/72V265 and the IDT72V275/ 72V285 SuperSync FIFOs • 10ns read/write ...
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IDT72V295/72V2105 3.3V HIGH DENSITY CMOS TM SUPERSYNC FIFO 131,072 x 18, 262,144 x 18 DESCRIPTION (CONTINUED) thus longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. • ...
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IDT72V295/72V2105 3.3V HIGH DENSITY CMOS TM SUPERSYNC FIFO 131,072 x 18, 262,144 IDT Standard mode, the first word written to an empty FIFO will not appear on the data output lines unless a specific read operation is ...
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IDT72V295/72V2105 3.3V HIGH DENSITY CMOS TM SUPERSYNC FIFO 131,072 x 18, 262,144 x 18 PIN DESCRIPTION Symbol Name D –D Data Inputs 0 17 MRS Master Reset PRS Partial Reset RT Retransmit FWFT/SI First Word Fall Through/Serial In WCLK Write ...
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IDT72V295/72V2105 3.3V HIGH DENSITY CMOS TM SUPERSYNC FIFO 131,072 x 18, 262,144 x 18 ABSOLUTE MAXIMUM RATINGS Symbol Rating V (2) Terminal Voltage TERM with respect to GND T Storage STG Temperature I DC Output Current OUT NOTES: 1. Stresses ...
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IDT72V295/72V2105 3.3V HIGH DENSITY CMOS TM SUPERSYNC FIFO 131,072 x 18, 262,144 ELECTRICAL CHARACTERISTICS (Commercial 3.3V ± 0.3V 0°C to +70°C; Industrial Symbol Parameter f Clock Cycle Frequency S t ...
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IDT72V295/72V2105 3.3V HIGH DENSITY CMOS TM SUPERSYNC FIFO 131,072 x 18, 262,144 x 18 FUNCTIONAL DESCRIPTION TIMING MODES: IDT STANDARD vs FIRST WORD FALL THROUGH (FWFT) MODE The IDT72V295/72V2105 support two different timing modes of opera- tion: IDT Standard mode ...
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IDT72V295/72V2105 3.3V HIGH DENSITY CMOS TM SUPERSYNC FIFO 131,072 x 18, 262,144 x 18 PROGRAMMING FLAG OFFSETS Full and Empty Flag offset values are user programmable. The IDT72V295/72V2105 has internal registers for these offsets. Default set- tings are stated in ...
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IDT72V295/72V2105 3.3V HIGH DENSITY CMOS TM SUPERSYNC FIFO 131,072 x 18, 262,144 x 18 IDT72V295 (131,072 x 18-BIT EMPTY OFFSET (LSB) REGISTER DEFAULT VALUE 007FH LOW at Master Reset, 03FFH HIGH ...
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IDT72V295/72V2105 3.3V HIGH DENSITY CMOS TM SUPERSYNC FIFO 131,072 x 18, 262,144 x 18 SERIAL PROGRAMMING MODE If Serial Programming mode has been selected, as described above, then programming of PAE and PAF values can be achieved by using a ...
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IDT72V295/72V2105 3.3V HIGH DENSITY CMOS TM SUPERSYNC FIFO 131,072 x 18, 262,144 FWFT mode is selected, the FIFO will mark the beginning of the Retransmit setup by setting OR HIGH. During this period, the internal read pointer ...
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IDT72V295/72V2105 3.3V HIGH DENSITY CMOS TM SUPERSYNC FIFO 131,072 x 18, 262,144 x 18 SIGNAL DESCRIPTION INPUTS: DATA Data inputs for 18-bit wide data. CONTROLS: MASTER RESET ( MRS ) A Master Reset ...
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IDT72V295/72V2105 3.3V HIGH DENSITY CMOS TM SUPERSYNC FIFO 131,072 x 18, 262,144 x 18 When WEN is HIGH, no new data is written in the RAM array on each WCLK cycle. To prevent data overflow in the IDT Standard mode, ...
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IDT72V295/72V2105 3.3V HIGH DENSITY CMOS TM SUPERSYNC FIFO 131,072 x 18, 262,144 x 18 EF/OR is synchronous and updated on the rising edge of RCLK. In IDT Standard mode double register-buffered output. In FWFT mode ...
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IDT72V295/72V2105 3.3V HIGH DENSITY CMOS TM SUPERSYNC FIFO 131,072 x 18, 262,144 x 18 MRS REN WEN t FWFT FWFT/ SEN EF/OR FF/IR PAE PAF COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES t RS ...
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IDT72V295/72V2105 3.3V HIGH DENSITY CMOS TM SUPERSYNC FIFO 131,072 x 18, 262,144 x 18 PRS REN WEN RT SEN EF/OR FF/IR PAE PAF COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES RSS t RSS ...
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IDT72V295/72V2105 3.3V HIGH DENSITY CMOS TM SUPERSYNC FIFO 131,072 x 18, 262,144 WRITE WCLK 1 (1) t SKEW1 WEN RCLK t t ENS ENH REN ...
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IDT72V295/72V2105 3.3V HIGH DENSITY CMOS TM SUPERSYNC FIFO 131,072 x 18, 262,144 x 18 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES 18 ...
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IDT72V295/72V2105 3.3V HIGH DENSITY CMOS TM SUPERSYNC FIFO 131,072 x 18, 262,144 x 18 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES 19 ...
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IDT72V295/72V2105 3.3V HIGH DENSITY CMOS TM SUPERSYNC FIFO 131,072 x 18, 262,144 x 18 RCLK t ENH t ENS t RTS REN WCLK t RTS WEN t ENS RT EF PAE ...
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IDT72V295/72V2105 3.3V HIGH DENSITY CMOS TM SUPERSYNC FIFO 131,072 x 18, 262,144 x 18 RCLK t t ENS ENH t RTS REN WCLK t RTS WEN t ENS RT OR PAE HF PAF ...
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IDT72V295/72V2105 3.3V HIGH DENSITY CMOS TM SUPERSYNC FIFO 131,072 x 18, 262,144 CLK t t CLKH CLKL WCLK t LDS LD t ENS WEN PAE OFFSET (LSB) Figure 14. Parallel ...
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IDT72V295/72V2105 3.3V HIGH DENSITY CMOS TM SUPERSYNC FIFO 131,072 x 18, 262,144 CLKH t CLKL WCLK t ENS t ENH WEN (2) n words in FIFO , PAE (3) n+1 words in FIFO (4) t SKEW2 RCLK ...
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IDT72V295/72V2105 3.3V HIGH DENSITY CMOS TM SUPERSYNC FIFO 131,072 x 18, 262,144 x 18 OPTIONAL CONFIGURATIONS WIDTH EXPANSION CONFIGURATION Word width may be increased simply by connecting together the control signals of multiple devices. Status flags can be detected from ...
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IDT72V295/72V2105 3.3V HIGH DENSITY CMOS TM SUPERSYNC FIFO 131,072 x 18, 262,144 x 18 FWFT/SI FWFT/SI WRITE CLOCK WCLK WRITE ENABLE WEN IDT INPUT READY IR 72V295 72V2105 n DATA IN Dn Figure 20. Block Diagram of 262,144 x 18 ...
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ORDERING INFORMATION XXXXX X XX Dev ower Speed NOTE: 1. Industrial temperature range is available as a standard device for 15ns. DATASHEET DOCUMENT HISTORY 9/12/2000 pg. 5. 12/18/2000 pgs and 26. 03/27/2001 pgs. ...