HMP8170CN Intersil Corporation, HMP8170CN Datasheet - Page 20

• Manufacturer Part Number: HMP8170CN
• Description: NTSC/PAL Video Encoder
• Manufacturer: Intersil Corporation

NUMBER
NUMBER
NUMBER
NUMBER
NUMBER
BIT
BIT
BIT
BIT
BIT
7-6
5-0
7-0
7-2
1-0
7-0
7-0
Reserved
Line 283
WSS CRC Data
LSB Assert BLANK
Output Signal
(Horizontal)
Reserved
MSB Assert BLANK
Output Signal
(Horizontal)
Negate BLANK
Output Signal
(Horizontal)
LSB Assert BLANK
Output Signal
(Vertical)
FUNCTION
FUNCTION
FUNCTION
FUNCTION
FUNCTION
20
This register is read out serially after the 14 bits of NTSC WSS data, if WSS is enabled. It is
ignored during PAL WSS operation. Bit D0 is shifted out first.
This 8-bit register is cascaded with Start H_Blank High Register to form a 10-bit
start_horizontal_blank register. It specifies the horizontal count (in 1x clock cycles) at which to
start ignoring pixel data each scan line. The leading edge of HSYNC is count 020
register is ignored unless BLANK is configured as an output.
This 2-bit register is cascaded with Start H_Blank Low Register to form a 10-bit
start_horizontal_blank register. It specifies the horizontal count (in 1x clock cycles) at which to
start ignoring pixel data each scan line. The leading edge of HSYNC is count 020
register is ignored unless BLANK is configured as an output.
This 8-bit register specifies the horizontal count (in 1x clock cycles) at which to start inputting
pixel data each scan line. The leading edge of HSYNC is count 000
unless BLANK is configured as an output.
This 8-bit register is cascaded with Start V_Blank High Register to form a 9-bit
start_vertical_blank register. During normal operation, it specifies the line number (n) to start
ignoring pixel input data (and what line number to start blanking the output video) each odd
field; for even fields, it occurs on line (n + 262) or (n + 313).
The leading edge of VSYNC at the start of an odd field is count 000
follow standard NTSC or PAL line numbering). This register is ignored unless BLANK is
configured as an output.
HMP8170, HMP8171, HMP8172, HMP8173
TABLE 35. START H_BLANK HIGH REGISTER
TABLE 34. START H_BLANK LOW REGISTER
TABLE 37. START V_BLANK LOW REGISTER
TABLE 36. END H_BLANK REGISTER
TABLE 33. CRC_283 REGISTER
SUB ADDRESS = 19
SUB ADDRESS = 20
SUB ADDRESS = 21
SUB ADDRESS = 22
SUB ADDRESS = 23
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
H
H
H
H
H
H
H
. This register is ignored
(note that this does not
H
H
. This
. This
111111
000000
RESET
RESET
RESET
RESET
RESET
STATE
STATE
STATE
STATE
STATE
4A
7A
00
11
03
B
B
H
H
H
B
B