HMP8190CN Intersil Corporation, HMP8190CN Datasheet - Page 19
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HMP8190CN
Manufacturer Part Number
HMP8190CN
Description
NTSC/PAL Video Encoder
Manufacturer
Intersil Corporation
Datasheet
1.HMP8190CN.pdf
(32 pages)
NUMBER
NUMBER
NUMBER
NUMBER
NUMBER
BIT
BIT
BIT
BIT
BIT
7-6
5-0
7-6
5-0
7-0
7-2
1-0
7-0
Reserved
Line 20
WSS CRC Data
Reserved
Line 283
WSS CRC Data
LSB Assert BLANK
Output Signal
(Horizontal)
Reserved
MSB Assert BLANK
Output Signal
(Horizontal)
Negate BLANK
Output Signal
(Horizontal)
FUNCTION
FUNCTION
FUNCTION
FUNCTION
FUNCTION
19
This register is read out serially after the 14 bits of NTSC WSS data, if WSS is enabled. It is
ignored during PAL WSS operation. Bit D0 is shifted out first.
This register is read out serially after the 14 bits of NTSC WSS data, if WSS is enabled. It is
ignored during PAL WSS operation. Bit D0 is shifted out first.
This 8-bit register is cascaded with Start H_Blank High Register to form a 10-bit
start_horizontal_blank register. It specifies the horizontal count (in 1x clock cycles) at which to
start ignoring pixel data each scan line. The leading edge of HSYNC is count 020
ister is ignored unless BLANK is configured as an output.
This 2-bit register is cascaded with Start H_Blank Low Register to form a 10-bit
start_horizontal_blank register. It specifies the horizontal count (in 1x clock cycles) at which to
start ignoring pixel data each scan line. The leading edge of HSYNC is count 020
ister is ignored unless BLANK is configured as an output.
This 8-bit register specifies the horizontal count (in 1x clock cycles) at which to start inputting
pixel data each scan line. The leading edge of HSYNC is count 000
unless BLANK is configured as an output.
TABLE 33. START H_BLANK HIGH REGISTER
TABLE 32. START H_BLANK LOW REGISTER
TABLE 34. END H_BLANK REGISTER
TABLE 31. CRC_283 REGISTER
TABLE 30. CRC_20 REGISTER
HMP8190, HMP8191
SUB ADDRESS = 18
SUB ADDRESS = 19
SUB ADDRESS = 20
SUB ADDRESS = 21
SUB ADDRESS = 22
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
H
H
H
H
H
H
. This register is ignored
H
H
. This reg-
. This reg-
111111
111111
000000
RESET
RESET
RESET
RESET
RESET
STATE
STATE
STATE
STATE
STATE
4A
7A
00
00
11
B
B
B
H
H
B
B
B