MT28F004B3VG-8BET Micron, MT28F004B3VG-8BET Datasheet - Page 13

• Manufacturer Part Number: MT28F004B3VG-8BET
• Description: 512K x 8 3V only, dula supply, smart 3 boot block flash memory
• Manufacturer: Micron

ERASE SEQUENCE
block to logic 1. The command sequence necessary to
execute an ERASE is similar to that of a WRITE. To provide
added security against accidental block erasure, two con-
secutive command cycles are required to initiate an ERASE
of a block. In the first cycle, addresses are “Don’t Care,”
and ERASE SETUP (20h) is given. In the second cycle, V
must be brought to V
be erased must be issued, and ERASE CONFIRM (D0h)
must be given. If a command other than ERASE CON-
FIRM is given, the write and erase status bits (SR4 and
SR5) are set, and the device is in the status register read
mode.
starts the ERASE of the addressed block. Any READ op-
eration outputs the status register contents on DQ0–
DQ7. V
pleted (SR7 = 1). When the ERASE is completed, the
device is in the status register read mode until another
command is issued. Erasing the boot block also requires
that either the RP# pin be set to V
held HIGH at the same time V
NOTE: 1. SR3-SR5 must be cleared using CLEAR STATUS REGISTER.
4Mb Smart 3 Boot Block Flash Memory
F45_3.p65 – Rev. 3, Pub. 12/01
SR5
Executing an ERASE sequence sets all bits within a
After the ERASE CONFIRM (D0h) is issued, the ISM
0
0
0
0
1
1
1
1
STATUS BITS
PP
must be held at V
SR4
0
0
1
1
0
0
1
1
SR3
PPH
0
1
0
1
0
1
0
1
, an address within the block to
PPH
ERROR DESCRIPTION
No errors
V
WRITE error
WRITE error, V
ERASE error
ERASE error, V
Command sequencing error or WRITE/ERASE error
Command sequencing error, V
PP
Status Register Error Code Description
PP
until the ERASE is com-
is set to V
voltage error
HH
or the WP# pin be
PPH
PP
PP
.
voltage not valid at time of ERASE CONFIRM
voltage not valid at time of WRITE
SMART 3 BOOT BLOCK FLASH MEMORY
PP
Table 4
13
PP
ERASE SUSPENSION
is in progress is ERASE SUSPEND. This command en-
ables other commands to be executed while pausing the
ERASE in progress. When the device has reached the
erase suspend mode, the erase suspend status bit (SR6)
and ISM status bit (SR7) are set. The device may now be
given a READ ARRAY, ERASE RESUME or READ STATUS
REGISTER command. After READ ARRAY has been is-
sued, any location not within the block being erased may
be read. If ERASE RESUME is issued before SR6 has been
set, the device immediately proceeds with the ERASE in
progress.
ERROR HANDLING
(SR3), write (SR4) and erase (SR5) status bits may be
checked. If one or a combination of these three bits has
been set, an error has occurred. The ISM cannot reset
these three bits. To clear these bits, CLEAR STATUS REG-
ISTER (50h) must be given. If the V
further WRITE or ERASE operations cannot resume until
the status register is cleared. Table 4 lists the combina-
tion of errors.
voltage error, with WRITE and ERASE errors
The only command that may be issued while an ERASE
After the ISM status bit (SR7) has been set, the V
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1
PP
status bit (SR3) is set,
©2001, Micron Technology, Inc.
4Mb
PP