MT9085B Zarlink Semiconductor, Inc., MT9085B Datasheet
MT9085B
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MT9085B Summary of contents
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... Mbit 4.096 Mbit/s. The PAC generates all framing signals required by the SMX for 1024 and 2048 channel configurations. Address Decoder VSS VDD Figure 1 - Functional Block Diagram MT9085B ISSUE 4 March 1999 Ordering Information MT9085BP 68 Pin PLCC -40 ° ° • • P7 C4i F0i C16i Timing C2o ...
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... MT9085B VSS S8 S9 S10 S11 S12 S13 VDD VSS S14 S15 S16 S17 S18 S19 S20 S21 2-126 Figure 2 - Pin Connections MCB 58 VSS C2o 55 C4o 54 DFPo 53 VDD 52 VSS 51 C16i 50 F0i 49 F0o ...
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... Connect Memory Frame Pulse (Output). Framing signal with a nominal 8 kHz frequency; goes low 71 (CKD= (CKD=1) C16 clock cycles before the frame boundary established by F0i. The signal is used by the connection memory in a typical switch configuration. See Figure 15 for timing information. Description for normal device operation. SS MT9085B 2-127 ...
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... MT9085B Pin Description (continued) Pin # Name 48 DFPo Data Memory Frame Pulse (Output). Framing signal with nominal 4 kHz frequency; changes state 64 (CKD= (CKD=1) C16 clock cycles after the frame boundary established by F0i. This signal is a complement of DFPo. See Figure 15 for timing information. The signal is used by SMXs (MT9080s) making up the Data Memory in a typical switch confi ...
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... Frame Boundary Established by F0i Ch. 31 Bit 0 Ch. 0 Bit 7 Ch. 63 Bit 0 Ch. 0 Bit 7 Frame Boundary Established by F0i Ch. 31 Bit 0 Ch. 0 Bit 7 Ch. 63 Bit 0 Ch. 0 Bit 7 MT9085B Ch. 0 Bit 6 Ch. 0 Bit 6 Ch. 0 Bit 5 Ch. 0 Bit 6 Ch. 0 Bit 6 Ch. 0 Bit 5 2-129 ...
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... MT9085B Frame Boundary established by F0i C16i CKD=0 Serial Output Ch. 31, Bit 0 S0-S31 Parallel Input MCB Parallel Input MCB CKD=1 Serial Ch. 31, Bit 0 Output S0-S31 Parallel Input ...
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... Y Figure 7 - Functional Data I/O Timing in Serial to Parallel Mode (MCA = 0) Ch. 0, Bit MT9085B Ch.0 Bit 2-131 ...
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... MT9085B Functional Description The MT9085 Parallel Access Circuit (PAC pin monolithic device. It interfaces a parallel 8 bit, time division, multiplexed bus time division multiplexed serial streams. The device can be configured to perform either parallel to serial conversion or serial to parallel conversion. A single PAC device can handle 1024 channels ...
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... SMX#1 is operated in Data Memory Mode-1. When the SMX is operated in Data Memory Mode-2, the maximum delay is two frames. In this case, the channels are double buffered; frame integrity is maintained for all switching configurations. MT9085B PAC #2 is configured to delay through the ...
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... MT9085B In the example configuration shown in Figure 9 the OE pin of PAC #2 is connected to D10 on the Connection Memory. Setting bit 10 high in the Connection Memory location corresponding to a serial channel timeslot will result in the output driver for the specific stream being disabled during that serial channel timeslot ...
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... For more information, see Zarlink’s Application Note MSAN-135, “Design of Large Digital Switching Matrices using the SMX/PAC“ (in this data book) and Application Sheet MSAS-62 “16.384 MHz Clock Generation for SMX/PAC“ (available from Zarlink). MT9085B ...
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... MT9085B Timing Source M4 C16 F0i C4i C16i PAC#1a S P0-P7 • • C16 • • • • • • S31 DFPo S31 DFPo 2/4S OE CKD MCA MCB F0 C4 C16 F0i C4i C16i PAC#1b S P0-P7 • • • • • • S31 • ...
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... MT9085B Min Max Units -0 -0 -0 °C -40 125 2 ) unless otherwise stated. SS Units Test Conditions ° Max Units Test Conditions 50 mA Outputs unloaded ...
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... MT9085B AC Electrical Characteristics Voltages are with respect to Ground (V ) unless otherwise stated. SS Characteristics 1 C16 Clock Period 2 C4 Clock Period 3 C16 Pulse Width Low 4 C16 Pulse Width High 5 C4 Setup Time 6 Frame Pulse Setup Time 7 Frame Pulse Hold Time † Timing is over recommended temperature & power supply voltages. ...
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... Data Memory and Connect Memory Frame Pulse (See ) unless otherwise stated. SS ‡ Sym Min Typ Max DFPo CFPo 71 C16 Cycles t CFPD t CFPD t CFPo MT9085B Units Test Conditions ST-BUS Frame Boundary Established by F0i 64 C16 Cycles t DFPo t DFPo 68 C16 Cycles t DFPo ...
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... MT9085B AC Electrical Characteristics (See Figure 16) - Voltages are with respect to Ground (V Characteristics 1 Serial Input Setup Time 2 Serial Input Hold Time 3 Serial Output Delay Active to Active High Impedance to Active Active to High Impedance † Timing is over recommended temperature & power supply voltages ° ‡ Typical figures are and are for design aid only: not guaranteed and not subject to production testing ...
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... Serial Input and Output Timing in 4 MHz Mode (2/4S=1) ) unless otherwise stated. SS ‡ Sym Min Typ Max Serial Bit Cell MT9085B Units Test Conditions =150pF =150pF =150pF 2-141 ...
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... MT9085B AC Electrical Characteristics to Ground (V ) unless otherwise stated. SS Characteristics 1 Parallel Output Delay 2 Parallel Output Delay High Impedance to Active 3 Parallel Output Delay Active to High Impedance † Timing is over recommended temperature & power supply voltages ° ‡ Typical figures are and are for design aid only: not guaranteed and not subject to production testing. ...
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... PZA 90% 10% t PZA † - Output Enable (OE) Timing, in Parallel to Serial Mode ) unless otherwise stated. SS ‡ Sym Min Typ Max t 2 OES t 10 OEH t OES t OEH t OEH MT9085B Units Test Conditions ns C =85pF =85pF L Units Test Conditions OES t OEH t OES 2-143 ...
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Package Outlines Dim D General- (lead coplanarity) A Notes Not ...
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North America - West Coast Tel: (858) 675-3400 Fax: (858) 675-3450 Tel: +65 333 6193 Fax: +65 333 6192 Information relating to products and services furnished herein by Zarlink Semiconductor Inc. trading as Zarlink Semiconductor or its subsidiaries (collectively “Zarlink”) ...