MT8888CP Zarlink Semiconductor, Inc., MT8888CP Datasheet - Page 12

• Manufacturer Part Number: MT8888CP
• Description: DTMF Transmitter, 28-PLCC
• Manufacturer: Zarlink Semiconductor, Inc.

11.0
The internal clock circuit is completed with the addition of a standard television colour burst crystal. The crystal
specification is as follows:
Frequency:
Frequency Tolerance:
Resonance Mode:
Load Capacitance:
Maximum Series Resistance: 150 ohms
Maximum Drive Level:
e.g.
A number of MT8888C devices can be connected as shown in Figure 13 such that only one crystal is required.
Alternatively, the OSC1 inputs on all devices can be driven from a TTL buffer with the OSC2 outputs left
unconnected.
12.0
The MT8888C incorporates an Intel microprocessor interface which is compatible with fast versions (16 MHz) of the
80C51. No wait cycles need to be inserted.
Figure 19 and Figure 20 are the timing diagrams for the Intel 8031, 8051 and 8085 (5 MHz) microcontrollers. By
NANDing the address latch enable (ALE) output with the high-byte address (P2) decode output, CS is generated.
Figure 14 summarizes the connection of these Intel processors to the MT8888C transceiver.
The microprocessor interface provides access to five internal registers. The read-only Receive Data Register
contains the decoded output of the last valid DTMF digit received. Data entered into the write-only Transmit Data
Register will determine which tone pair is to be generated (see Table 1 for coding details). Transceiver control is
accomplished with two control registers (see Table 6 and Table 7), CRA and CRB, which have the same address. A
write operation to CRB is executed by first setting the most significant bit (b3) in CRA. The following write operation
to the same address will then be directed to CRB, and subsequent write cycles will be directed back to CRA. The
read-only status register indicates the current transceiver state (see Table 8).
A software reset must be included at the beginning of all programs to initialize the control registers upon power-up
or power reset (see Figure 19). Refer to Tables 4-7 for bit descriptions of the two control registers.
CTS Knights MP036S
Toyocom
DTMF Clock Circuit
Microprocessor Interface
TQC-203-A-9S
3.579545 MHz
Parallel
18pF
2mW
0.1%
OSC1 OSC2
3.579545 MHz
MT8888C
Figure 13 - Common Crystal Connection
Zarlink Semiconductor Inc.
MT8888C
OSC1 OSC2
MT8888C
12
OSC1 OSC2
MT8888C
Data Sheet