MT88E43AS Zarlink Semiconductor, Inc., MT88E43AS Datasheet - Page 7

• Manufacturer Part Number: MT88E43AS
• Description: Extended Voltage Calling Number Identification Circuit 2
• Manufacturer: Zarlink Semiconductor, Inc.

Data Sheet
FSK Demodulation
The MT88E43 first bandpass filters and then
demodulates the incoming FSK signal. The carrier
detector provides an indication of the presence of
signal at the bandpass filter output. The MT88E43’s
dual mode 3-wire interface allows convenient
extraction of the 8-bit data words in the demodulated
FSK bit stream.
Note that signals such as dual tone alert signal,
speech and DTMF tones lie in the same frequency
band as FSK. They will, therefore, be demodulated
and as a result, false data will be generated. To
avoid demodulation of false data, an FSKen pin is
provided so that the FSK demodulator may be
disabled when FSK signal is not expected. There are
two events that if either is true, should be used to
disable FSKen. The events are CD returning high or
receiving all the data indicated by the message
length word.
Differential Input Amplifier
Voltage Gain
(A
C1 = C2
R1 = R4 (For unity gain R5= R4)
R3 = (R2R5) / (R2 + R5)
Input Impedance
(Z
Voltage Gain
(A
V
IN
V
diff) = R5/R1 (see Figure 9,10,11)
) = R
diff) = 2
Figure 7 - Differential Input Configuration
C
C1
C2
F
/ R
Figure 6 - Single-Ended Input
IN
R1
R
R1
R4
IN
2
+ (1/ C)
R3
Configuration
2
R2
R
R5
F
IN+
IN-
GS
V
V
GS
IN+
IN-
Ref
Ref
The FSK characteristics described in Table 2 are listed
in BT and Bellcore specifications. The BT signal
frequencies correspond to CCITT V.23. The Bellcore
frequencies correspond to Bell 202. The U.K.’s CCA
requires that the TE be able to receive both CCITT
V.23 and Bell 202, as specified in the BT and Bellcore
specifications. The MT88E43 is compatible with both
formats without any adjustment.
•
The MT88E43 provides a powerful dual mode 3-wire
interface so that the 8-bit data words in the
demodulated FSK bit stream can be extracted
without the need either for an external UART or for
the TE/CPE’s microcontroller to perform the UART
function in software. The interface is specifically
designed for the 1200 baud rate and is comprised of
the DATA, DCLK (data clock) and DR (data ready)
pins. Two modes (modes 0 and 1) are selectable via
control of the device’s MODE pin: in mode 0, data
a. The signal power is expressed in dBm referenced to 600
b. SR-3004,Issue 2, January 1995.
c. The frequency range is specified in GR-30-CORE.
d. Up to 20 marks may be inserted in specific places in a single
Mark
frequency
(logic 1)
Space
frequency
(logic 0)
Received
signal level -
mark
Received
signal level -
space
Signal level
differential
(twist)
Unwanted
signals
Transmission
rate
Word format
ohm at the CPE tip/ring (A/B) interface.
or multiple data message.
3-wire User Interface
Item
Table 2 - FSK Characteristics
1 start bit (logic
(LSB first), 1 to
(300-3400Hz)
(-5.78dBm to
0), 8 bit word
-37.78dBm)
10 stop bits
1200 baud
up to 6dB
<= -20dB
-8dBV to
-8dBV to
(logic 1)
1300Hz
2100Hz
-40dBV
-40dBV
1.5%
1.5%
± 1%
BT
MT88E43
1 start bit (logic
0), 8 bit word
up to 10dB
-12dBm
1200 baud
(LSB first),
-12dBm to
<= -25dB
1 stop bit
(logic 1)
Bellcore
-32dBm
-36dBm
1200Hz
2200Hz
(0-4kHz)
± 1%
1%
1%
a
to
d
b
c
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