MT8966AS Zarlink Semiconductor, Inc., MT8966AS Datasheet - Page 2
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MT8966AS
Manufacturer Part Number
MT8966AS
Description
CODEC, MuLaw CODEC, Single Channel Integrated PCM Filter CODEC, 20SOIC
Manufacturer
Zarlink Semiconductor, Inc.
Datasheet
1.MT8966AS.pdf
(24 pages)
Available stocks
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Part Number
Manufacturer
Quantity
Price
Part Number:
MT8966AS
Manufacturer:
MITEL
Quantity:
20 000
MT8960/61/62/63/64/65/66/67
6-20
Pin Description
Pin Name
GNDD
SD4-5
SD0-2
GNDA
ANUL
DSTo
CSTi
DSTi
SD3
V
V
V
C2i
F1i
CA
V
V
DD
Ref
EE
R
X
Control ST-BUS In is a TTL-compatible digital input used to control the function of the filter/codec.
Three modes of operation may be effected by applying to this input a logic high (V
(GNDD), or an 8-bit serial word, depending on the logic states of CA and F1i.
Functions controlled are: powerdown, filter gain adjust, loopback, chip testing, SD outputs.
Data ST-BUS In accepts the incoming 8-bit PCM word. Input is TTL-compatible.
Clock Input is a TTL-compatible 2.048 MHz clock.
Data ST-BUS Out is a three-state digital output driving the PCM bus with the outgoing 8-bit PCM
word.
Positive power Supply (+5V).
Synchronization Input is an active low digital input enabling (in conjunction with CA) the PCM input,
PCM output and digital control input. It is internally sampled on every positive edge of the clock, C2i,
and provides frame and channel synchronization.
Control Address is a three-level digital input which enables PCM input and output and determines
into which control register (A or B) the serial data, presented to CSTi, is stored.
System Drive Output is an open drain output of an N-channel transistor which has its source tied to
GNDA. Inactive state is open circuit.
System Drive Outputs are open drain outputs of N-channel transistors which have their source tied
to GNDD. Inactive state is open circuit.
System Drive Outputs are “Totempole“ CMOS outputs switching between GNDD and V
state is logic low.
Negative power supply (-5V).
Voice Transmit is the analog input to the transmit filter.
Auto Null is used to integrate an internal auto-null signal. A 0.1 µ F capacitor must be connected
between this pin and GNDA.
Voice Receive is the analog output of the receive filter.
Analog ground (0V).
Voltage Reference input to D to A converter.
Digital ground (0V).
DSTo
CSTi
DSTi
VDD
SD3
SD2
C2i
F1i
CA
18 PIN CERDIP/PDIP
MT8960/61/64/65
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
Figure 2 - Pin Connections
GNDD
VRef
GNDA
VR
ANUL
VX
VEE
SD0
SD1
Description
ISO
2
DSTo
CSTi
DSTi
-CMOS
VDD
SD5
SD4
SD3
C2i
F1i
CA
20 PIN PDIP/SOIC
MT8962/63/66/67
10
1
2
3
4
5
6
7
8
9
20
19
18
17
16
15
14
13
12
11
GNDD
VRef
GNDA
VR
ANUL
VX
VEE
SD0
SD1
SD2
DD
), logic low
DD
. Inactive