MT8986 Mitel Semiconductor, MT8986 Datasheet - Page 21

• Manufacturer Part Number: MT8986
• Description: CMOS ST-BUS FAMILY Multiple Rate Digital Switch
• Manufacturer: Mitel Semiconductor

throughput
applications,
effective implementations of Non-Blocking matrices
ranging up to 1024 channels. Figures 12 and 13
show the block diagram of implementations with
Non-Blocking capacities of 512 and 1024-channel,
respectively.
Interfacing MT8986 with 8051
The Intel 8051 is a very cost effective solution for
many applications that do not require a large CPU
interaction and processing overhead. However, in
applications where 8051 is connected to peripherals
operating on a synchronous 8 kHz time-base like the
MT8986, some connectivity issues have to be
addressed. The MT8986 may hold the CPU read/
write cycle due to internal contention between the
MT8986 microport and the internal serial to parallel
Figure 12 - 512-Channel Non-Blocking Switch Matrix with Serial Streams at 2.048 or 4.096 Mb/s
IN
IN
IN
Figure 13 - 1024-Channel Non-Blocking Switch Matrix with Serial Streams at 2.048 Mb/s
@2.048 Mb/s
@2.048 Mb/s
@2.048 Mb/s
16 Streams
16 Streams
16 Streams
16
delay
the
MT8986
is
512 x 256
512 x 256
16
16
MT8986
MT8986
guaranteed.
device
512 x 256
512 x 256
512 x 256
512 x 256
MT8986
MT8986
MT8986
MT8986
8
8
@2.048 Mb/s
@2.048 Mb/s
allows
8 Streams
8 Streams
For
OUT
such
cost
and parallel to serial converters. Since the 8051
family of CPUs do not provide Data Ready type of
inputs,
intervention have to be provided between the
MT8986 and the 8051 microcontrollers to allow read/
write operation. The external logic described in
Figure 14 is a block diagram of a logical connection
between MT8986 and 8051. Its main function is to
store the 8051 data during a write and the MT8986
data during a read.
For a write, MT8986 address is latched by the
internal address latch on the falling edge of the ALE
input. Whenever a read or write operation is done to
the MT8986 device, the address decoded signal
(MTA) is used to latch or "freeze" the state of RD,
WR, and the ALE signals, until the data acknow-
ledge output signal is provided by the MT8986
device, releasing the latches for a new read/write
cycle. Latch U5 is used to hold the 8051 data for a
write until the CPU is ready to accept it (when DTA
IN
@4.096 Mb/s
8 Streams
some
8
512 x 256
512 x 256
512 x 256
512 x 256
MT8986
MT8986
MT8986
MT8986
external
512 x 256
512 x 256
MT8986
MT8986
8
8
8
8
logic
@2.048 Mb/s
@2.048 Mb/s
@2.048 Mb/s
@2.048 Mb/s
8 Streams
8 Streams
8 Streams
8 Streams
and
4
4
@4.096 Mb/s
@4.096 Mb/s
MT8986
4 Streams
4 Streams
OUT
software
OUT
OUT
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