MT8986 Mitel Semiconductor, MT8986 Datasheet - Page 22

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MT8986

Manufacturer Part Number
MT8986
Description
CMOS ST-BUS FAMILY Multiple Rate Digital Switch
Manufacturer
Mitel Semiconductor
Datasheet

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MT8986
goes low). Latch U4 stores the MT8986 output data
during a read cycle whenever DTA goes low. When
writing to the MT8986, one write operation is
sufficient. However, when reading MT8986, two read
operations with the same address are required, with
the second being valid.
2-84
RES
RST
8051
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
ALE
WR
RD
8
Figure 14 - Interfacing the MT8986 to the 8051 Microcontroller
MT8986
Address
Decode
8
D
CK
D
CK
D
CK
CS
PR
PR
PR
Q
Q
Q
MT8986
Access
LRD
LWR
DTA
MTA
Enough time need to be provided between two CPU
accesses to allow the first access to complete; i.e.,
to allow for an internal MT8986 reaction over the first
RD/WR access. For a read operation, a minimum of
1220 ns have to be guaranteed between two
successive accesses. For write, at least 800 ns has
to be respected.
LE
LATCH
RES
OE
R
C
OE
LATCH
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
ALE
WR
RD
CS
LE
MT8986
DTA
DTA
AD0-AD7
RD
MTA
MTA

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