CA3290A Intersil, CA3290A Datasheet - Page 4

• Manufacturer Part Number: CA3290A
• Description: BiMOS Dual Voltage Comparators
• Manufacturer: Intersil

Test Circuits and Waveforms
Circuit Description
The Basic Comparator
Figure 4 shows the basic circuit diagram for one of the two
comparators in the CA3290. It is generically similar to the
industry type “139” comparators, with PMOS transistors
replacing PNP transistors as input stage elements. Transistors
Q
and Q
differential-to-single-ended converter. The differential input at
Q
the input signal polarity. For example, if +V
-V
turned off; Transistors Q
causing Q
when a load resistor is connected between the output and V+.
In essence, Q
Q
providing gate oxide protection against input voltage
transients (e.g., static electricity). The current flow in Q
1
1
2
IN
through Q
and Q
and Q
INPUT
, Q
INPUT
1K
1K
6
1
serving as a mirror connected active load and
, Q
1K
1K
4
3
8
, respectively, with zener diodes D
is amplified so as to toggle Q
2
to be turned off. The output is pulled positive
, and current mirror transistors Q
+
-
+15V
4
+
-
+15V
1
comprise the differential input stage, with Q
and Q
OUTPUT
OUTPUT
FIGURE 2. NON-INVERTING COMPARATOR RESPONSE TIME TEST CIRCUIT AND WAVEFORMS
5.1K
5.1K
FIGURE 3. INVERTING COMPARATOR RESPONSE TIME TEST CIRCUIT AND WAVEFORMS
4
3
function as source followers to drive
, Q
OVERDRIVE
OVERDRIVE
GND
GND
4
, and Q
INPUT
4
INPUT
OVERDRIVE
100mV
7
will be turned on,
6
OVERDRIVE
in accordance with
IN
is greater than
5
1
OVERDRIVE
and Q
through D
5mV
20mV
CA3290, CA3290A
6
OVERDRIVE
will be
1
and
20mV
4
5
5mV
OVERDRIVE
100mV
OVERDRIVE
Q
sources I
operated with a constant current load, their gate-to-source
voltage drops will be effectively constant as long as the input
voltages are within the common-mode range.
As a result, the input offset voltage (V
V
differential DC voltage is applied to the device for extended
periods of time at high temperatures.
Additional voltage gain following the first stage is provided by
transistors Q
the user a wide variety of options in applications. An
additional discrete transistor can be added if it becomes
necessary to boost the output sink current capability.
The detailed schematic diagram for one comparator and the
common current source biasing is shown on the front page.
PMOS transistors Q
elements identified in Figure 4 as I
BE(Q3)
4
is established at approximately 50 A by constant current
OVERDRIVE
OVERDRIVE
- V
GND
GND
1
and I
INPUT
GS(Q4)
INPUT
7
and Q
3
OVERDRIVE
OVERDRIVE
, respectively. Since Q
) will not be degraded when a large
9
8
100mV
through Q
. The collector of Q
5mV
20mV
OVERDRIVE
12
OVERDRIVE
1
are the current source
through I
20mV
GS(Q1)
1
8
and Q
is open, offering
5mV
OVERDRIVE
4
+ V
, respectively.
100mV
OVERDRIVE
4
BE(Q2)
are
-