CS4373 Cirrus Logic, CS4373 Datasheet
CS4373
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CS4373 Summary of contents
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... THD from the precision output, and -100 dB THD from the buffered output. Noise performance is 114 dB SNR over a 430 Hz bandwidth. The CS4373 has very low power consumption. In normal mode (LPWR=0; MCLK=2.048 MHz), power consumption is 40 mW; while in Low Pow- er mode (LPWR=1; MCLK=1.024 MHz), power consumption ...
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... Low Power Mode ............................................................................................................. 15 9.3 Sleep Mode ...................................................................................................................... 15 9.4 Power Down ..................................................................................................................... 15 10. POWER SUPPLY ................................................................................................................ 15 10.1 Power Supply Bypassing .............................................................................................. 15 10.2 SCR Latch-up Considerations ...................................................................................... 15 10.3 DC-DC Converter Considerations ................................................................................. 16 10.4 Power Supply Rejection ................................................................................................ 16 11. PIN DESCRIPTION ............................................................................................................... 17 12. ORDERING INFORMATION ................................................................................................ 19 13. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION .......................... 19 14. REVISION HISTORY ........................................................................................................... 19 15. PACKAGE DIMENSIONS ..................................................................................................... 20 2 CS4373 DS577F1 ...
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... LIST OF FIGURES Figure 2. Timing .............................................................................................................................. 7 Figure 1. Rise and Fall Times ......................................................................................................... 7 Figure 4. CS4373 System Connections .......................................................................................... 8 Figure 5. 2.5 Voltage Reference Circuit ........................................................................................ 11 Figure 6. Test Mode 1 ................................................................................................................... 13 Figure 7. Test Mode 4 ................................................................................................................... 13 Figure 8. Test Mode 5 ................................................................................................................... 14 LIST OF TABLES Table 1. Test Modes ..................................................................................................................... 13 Table 2. Attenuator Selection........................................................................................................ 15 Table 3. Attenuator Selection........................................................................................................ 18 Table 4. Mode Selection ............................................................................................................... 18 Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative ...
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... Dual Supply T A Symbol SNR Unloaded OUT SNR Unloaded BUF 1 kΩ load THD Unloaded OUT THD Unloaded BUF 1 kΩ load f TDATA BW FS (Note (Note CS4373 ° Min Typ Max Unit 3.135 3.3 5.25 V 4.75 5 5.25 V 2.375 2.5 2.625 V -0.25 0 0.25 V -2.625 -2.5 -2.375 ...
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... LPWR = 1; MCLK = 1.024 MHz Power Down Mode Sleep Mode 3. Specification is for the parameter over the specified temperature range and is for the CS4373 only and does not include the effects of external components 2.5 V voltage reference results in the highest dynamic range and best signal-to-noise performance, though smaller reference voltages may be used. 5. VREF is defined as {(VREF+) - (VREF-)} and Inputs must satisfy: VA- < ...
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... Symbol Positive Digital VD Positive Analog VA+ Negative Analog VA- (Note 11, 12 (Note 12 OUT (Note 13) PDS All Analog Pins V (VA-) - 0.5 INA All Digital Pins V IND stg CS4373 Min Typ Max Unit - VD V 0 ±1 ±10 µA Min Max Unit -0.3 +6.8 V -0.3 +6.8 V -3.3 +0 ± ± ...
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... Fall Times: Any Digital Input SYNC Setup Time to MCLK falling SYNC Hold Time after MCLK falling Notes: 14. If MCLK is removed, the CS4373 enters a sleep mode state. 15. SYNC latched on MCLK falling edge, data output on next MCLK rising edge. MCLK (2.048 MHz) MSYNC ...
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... CAP+ COG CAP- Switch BUF+ Control BUF- CS4373 OUT+ OUT- 10 Ω VREF+ VREF- VREF VA- 100µF 0.01µF VA- 0.01µF Figure 4. CS4373 System Connections CS4373 MCLK MCLK MSYNC MSYNC MDATA1 MDATA1 MFLAG1 MFLAG1 CS5372 MDATA2 MDATA2 MFLAG2 MFLAG2 LPWR CS5376A MCLK MSYNC MDATA1 ...
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... Offset Drift - The variation in the measured offset voltage across the specified temperature range. DS577F1 ( rms magnitude of full scale signal rms magnitude of noise floor sum of the powers of the harmonic frequencies ( power of the fundamental frequency theoretical attenuated voltage ( | measured offset theoretical full scale voltage CS4373 ( ( ( •100% ( •100 •100 ...
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... Signal Bitstream Input - TDATA TDATA is the test bitstream input for the CS4373 ∆Σ one’s density bitstream in- put at a rate of MCLK/8. The digital filter has a bitstream available on its TBSDATA pin. When used with the CS5376A/78, TDATA can be connected directly to TBSDATA for it’ ...
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... CS4373 uses a SYNC signal. When using the CS5376A/78 digital filters, SYNC is automatically generated from a SYNC signal input from the external system. The CS4373 SYNC input is rising edge trig- gered and resets the internal MCLK counter- divider. 6. VOLTAGE REFERENCE 6.1 Voltage Reference Inputs The CS4373 is designed to operate with a 2 ...
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... Gain Accuracy Gain accuracy of the CS4373 is affected by variations of the voltage reference input. A change in the voltage reference input imped- ance due to a change in MCLK could affect gain accuracy when using the higher source impedance configuration of VREF+ pin input impedance and the external ...
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... TEST MODES The CS4373 has 7 test modes. The MODE0, MODE1, and MODE2 pins define which mode the part will operate. Table 1 mode options and corresponding MODE pin settings. The following subsections explain the CS4373 Test Mode Options: MODE2 MODE1 Test Mode 0 ...
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... Linearity can also be measured from the out- put of OUT±. And when connected to the digi- tal filter, a digital impulse bitstream can be fed directly to the CS4373 to test the impulse re- sponse of the system. 7.3 Test Mode 2: Electronics Test Mode In this test mode, outputs BUF± are high-Z and only OUT± ...
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... Bypass capacitors can be X7R, tan- talum, or any other dielectric types. 10.2 SCR Latch-up Considerations The VA- pin is tied to the CS4373 CMOS sub- strate and should always be connected to the most negative supply voltage to ensure SCR latch-up does not occur. In general, latch-up may occur when any pin voltage (including the analog inputs ...
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... V above ground to ensure SCR latch-up does not occur during power up. If the VA+ power supply ramps before the VA- supply, the VA- voltage could be pulled above ground through the CS4373. If the VA- supply is unin- tentionally pulled 0.7 V above the DGND pin, SCR latch-up can occur. 10.3 DC-DC Converter Considerations ...
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... Power supply for the digital section. Refer to the Recommended Operating Conditions for appropri- ate voltages. LPWR 28 I Low Power Mode Select - When set high the CS4373 enters into a Low Power Mode. (See Section Section 9, "Power Modes" on page 15 TDATA 24 I Test DAC Signal Bitstream Input. ...
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... Table 3. Attenuator Selection Mode Reserved Sensor Test ± OUT ± BUF Common Mode High Voltage Reserved Reserved Chip Power Down Table 4. Mode Selection CS4373 ATT1 ATT0 MODE2 MODE1 MODE0 ...
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... MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020. 14.REVISION HISTORY Revision Date PP1 MAR 2003 Initial preliminary release. F1 SEP 2005 Final version. MSL data added. DS577F1 Temperature -40 to +85 °C Peak Reflow Temp MSL Rating* 240 °C Changes CS4373 Package 28-pin SSOP Max Floor Life 2 365 Days 19 ...
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... SIDE VIEW NOM MAX MIN -- 0.084 0.006 0.010 0.05 0.069 0.074 1.62 -- 0.015 0.22 0.4015 0.413 9.90 0.307 0.323 7.40 0.209 0.220 5.00 0.026 0.030 0.55 0.0354 0.041 0.63 4° 8° 0° JEDEC #: MO-150 Controlling Dimension is Millimeters 1 E1 ∝ END VIEW L MILLIMETERS NOM MAX -- -- 2.13 0.15 0.25 1.75 1.88 -- 0.38 10.20 10.50 7.80 8.20 5.30 5.60 0.65 0.75 0.90 1.03 4° 8° CS4373 NOTE 2 DS577F1 ...