CS4373 Cirrus Logic, CS4373 Datasheet - Page 11

• Manufacturer Part Number: CS4373
• Description: High-performance Delta-Sigma Test DAC
• Manufacturer: Cirrus Logic

5.3 Clock Sync Input - SYNC
To synchronize the timing of the digital input
bitstream, the CS4373 uses a SYNC signal.
When using the CS5376A/78 digital filters,
SYNC is automatically generated from a
SYNC signal input from the external system.
The CS4373 SYNC input is rising edge trig-
gered and resets the internal MCLK counter-
divider.
6. VOLTAGE REFERENCE
6.1 Voltage Reference Inputs
The CS4373 is designed to operate with a
2.5 V voltage reference applied across the
VREF+ and VREF- pins.
In a single supply power configuration the
VREF+ pin should be connected to the voltage
reference output, and the VREF- pin connect-
ed to ground. In a dual supply power configu-
ration the voltage reference should be
powered from the VA+ and VA- supplies, with
the VREF+ pin connected to the voltage refer-
ence output and the VREF- pin connected to
VA-. Because most 2.5 V voltage references
require a power supply voltage greater than
3 V to operate, when powering the voltage ref-
erence from dual ±2.5 V supplies the refer-
ence voltage into the VREF+ pin should be
DS577F1
VA+
VA-
Figure 5. 2.5 Voltage Reference Circuit
0.1 µ F
0.1 µ F
LT1019-2.5
2.5V REF
10 Ω
0.1 µ F
defined relative to the VA- supply (see
Figure
The selected voltage reference should pro-
duce less than 1 µVrms of noise in the mea-
surement bandwidth on the VREF+ pin. The
digital filter output word rate selection deter-
mines the bandwidth over which voltage refer-
ence noise affects the CS4373 dynamic
range.
6.2 Voltage Reference Configurations
For a 2.5 V reference, the Linear Technology
LT1019-2.5 voltage reference yields low
enough noise if the output is filtered with a low
pass RC filter as shown in
6.3 VREF Input Impedance
The switched-capacitor input architecture of
the VREF+ pin causes the input current re-
quired from the voltage reference to change
any time MCLK is changed. The input imped-
ance of the voltage reference input is calculat-
ed similar to the analog signal input
impedance as [1 / (f * C)] where f is the master
clock frequency, MCLK, and C is the internal
sampling capacitor. A 2.048 MHz MCLK yields
a voltage reference input impedance of ap-
proximately
about 24 kΩ.
+
100 µ F
5).
[1 / (2.048 MHz)*(20 pF)],
To VREF -
To VREF+
Figure
5.
CS4373
11
or