CS8405A Cirrus Logic, CS8405A Datasheet - Page 15

• Manufacturer Part Number: CS8405A
• Description: 96 KHZ DIGITAL AUDIO INTERFACE TRANSMITTER
• Manufacturer: Cirrus Logic

MAP byte. The MAP auto increment bit (INCR)
may be set or not, as desired. To begin a read, bring
CS low, send out the chip address and set the
read/write bit (R/W) high. The next falling edge of
CCLK will clock out the MSB of the addressed
register (CDOUT will leave the high impedance
state). If the MAP auto increment bit is set to 1, the
data for successive registers will appear consecu-
tively.
6.2
In Two-Wire Mode, SDA is a bidirectional data
line. Data is clocked into and out of the part by the
clock, SCL, with the clock to data relationship as
shown in Figure 9. There is no CS pin. Each indi-
vidual CS8405A is given a unique address. Pins
AD0, AD1, and AD2 form the three least signifi-
cant bits of the chip address, and should be con-
nected to VL+ or DGND as desired. The upper four
bits of the seven-bit address field are fixed at 0010.
To communicate with a CS8405A, the chip address
field, which is the first byte sent to the CS8405A,
should match 0010 followed by the settings of
AD2, AD1, and AD0. The eighth bit of the address
is the R/W bit. If the operation is a write, the next
byte is the Memory Address Pointer (MAP) which
selects the register to be read or written. If the op-
eration is a read, the contents of the register pointed
DS469PP4
Two-Wire
S D A
S C L
N o te 1 : A D 2 is d e riv e d fro m a re s is to r a tta c h e d to th e E M P H p in ,
N o te 2 : If o p e ra tio n is a w rite , th is b y te c o n ta in s th e M e m o ry A d d re s s P o in te r, M A P
N o te 3 : If o p e ra tio n is a re a d , th e la s t b it o f th e re a d s h o u ld b e a N A C K (h ig h )
S ta rt
Mode
A D 1 a n d A D 0 a re d e te rm in e d b y th e s ta te o f th e c o rre s p o n d in g p in s
0 0 1 0
Figure 9. Control Port Timing in Two-Wire Mode
A D 2 -0
N o te 1
R /W
A C K
to by the MAP will be output. Setting the auto in-
crement bit in MAP allows successive reads or
writes of consecutive registers. Each byte is sepa-
rated by an acknowledge bit, ACK, which is output
from the CS8405A after each input byte is read.
The ACK bit is input to the CS8405A from the mi-
crocontroller after each transmitted byte. The Two-
Wire Mode is compatible with the I
6.3
The CS8405A has a comprehensive interrupt capa-
bility. The INT output pin is intended to drive the
interrupt input pin on the host microcontroller. The
INT pin may be set to be active low, active high or
active low with no active pull-up transistor. This
last mode is used for active low, wired-OR hook-
ups, with multiple peripherals connected to the mi-
crocontroller interrupt input pin.
Many conditions can cause an interrupt, as listed in
the interrupt status register descriptions. Each
source may be masked off by a bit in the mask reg-
isters. In addition, each source may be set to rising
edge, falling edge, or level sensitive. Combined
with the option of level sensitive or edge sensitive
modes within the microcontroller, many different
set-ups are possible, depending on the needs of the
equipment designer.
D ATA 7 -0
Interrupts
N o te 2
A C K
D ATA 7 - 0
A C K
N o te 3
2
CS8405A
C protocol.
S to p
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