CS8405A Cirrus Logic, CS8405A Datasheet - Page 22

• Manufacturer Part Number: CS8405A
• Description: 96 KHZ DIGITAL AUDIO INTERFACE TRANSMITTER
• Manufacturer: Cirrus Logic

8.11
The two Interrupt Mode registers form a 2-bit code for each Interrupt Register 1 function. There are three ways to
set the INT pin active in accordance with the interrupt condition. In the Rising edge active mode, the INT pin be-
comes active on the arrival of the interrupt condition. In the Falling edge active mode, the INT pin becomes active
on the removal of the interrupt condition. In Level active mode, the INT interrupt pin becomes active during the in-
terrupt condition. Be aware that the active level (Active High or Low) only depends on the INT[1:0] bits. These reg-
isters default to 00.
8.12
Note:
22
7
7
0
0
0
Interrupt 2 Mode MSB (Dh) and Interrupt Mode 2 LSB(Eh)
Channel Status Data Buffer Control (12h)
BSEL - Selects the data buffer register addresses to contain User data or Channel Status data
There are separate complete buffers for the Channel Status and User bits. This control bit determines which
buffer appears in the address space.
EFTCI - E to F C-data buffer transfer inhibit bit.
CAM - C-data buffer control port access mode bit
00 - Rising edge active
01 - Falling edge active
10 - Level active
11 - Reserved
Default = ‘0’
0 - Data buffer address space contains Channel Status data
1 - Data buffer address space contains User data
Default = ‘0’
0 - Allow C-data E to F buffer transfers
1 - Inhibit C-data E to F buffer transfers
Default = ‘0’
0 - One byte mode
1 - Two byte mode
6
6
0
0
0
BSEL
5
5
0
0
4
0
0
4
0
3
0
0
3
0
EFTU1
EFTU0
EFTCI
2
2
CAM
1
0
0
1
CS8405A
DS469PP4
0
0
0
0
0