CS8421 Cirrus Logic, CS8421 Datasheet - Page 14

• Manufacturer Part Number: CS8421
• Description: 32-bit 192 kHz Asynchronous Sample Rate Converter
• Manufacturer: Cirrus Logic

14
Master Mode
I/OSCLK Frequency (non-TDM)
OSCLK Frequency (TDM)
I/OLRCK Duty Cycle
I/OSCLK Duty Cycle
I/OSCLK Falling Edge to I/OLRCK Edge
OSCLK Falling Edge to OLRCK Edge (TDM)
OSCLK Falling Edge to SDOUT Output Valid
SDIN/TDM_IN Setup Time Before I/OSCLK Rising Edge
SDIN/TDM_IN Hold Time After I/OSCLK Rising Edge
I/OLRCK
I/OSCLK
I/OSCLK
SDOUT
SDOUT
I/OLRCK
SDIN
(input)
(output)
SDIN
(output)
(output)
(input)
(input)
(input)
(output)
Figure 3. Non-TDM Master Mode Timing
6. After powering up the CS8421, RST should be held low until the power supplies and clocks are settled.
7. The maximum possible sample rate is XTI/128.
8. OLRCK must remain high for at least 8 OSCLK periods in TDM Mode.
9. Only the input or the output serial port can be set as master at a given time.
Figure 1. Non-TDM Slave Mode Timing
t
(Note 9)
lckd
t
lcks
t
dpd
t
dpd
t
lcks
t
ds
t
ds
Parameters
t
dh
t
MSB
MSB
dh
t
sckh
MSB
MSB
t
sckl
MSB-1
MSB-1
MSB-1
MSB-1
TDM_IN
OLRCK
SDOUT
OSCLK
(output)
(output)
(output)
(input)
TDM_IN
OLRCK
OSCLK
SDOUT
(output)
(input)
(input)
(input)
t
fss
t
fss
Figure 4. TDM Master Mode Timing
Figure 2. TDM Slave Mode Timing
Symbol
t
lrckh
t
t
t
lcks
dpd
t
t
fss
ds
dh
t
fsh
t
dpd
t
dpd
Min
45
45
t
3
5
ds
-
-
-
t
ds
256*Fso
64*Fsi/o
www.DataSheet4U.com
t
dh
t
dh
t
sckh
MSB
MSB
MSB
MSB
Max
55
55
5
5
7
-
-
CS8421
t
sckl
DS641F2
MSB-1
MSB-1
MSB-1
MSB-1
Units
MHz
MHz
ns
ns
ns
ns
ns
%
%