CS8421 Cirrus Logic, CS8421 Datasheet - Page 19

• Manufacturer Part Number: CS8421
• Description: 32-bit 192 kHz Asynchronous Sample Rate Converter
• Manufacturer: Cirrus Logic

DS641F2
Table 1. Serial Audio Port Master/Slave and Clock Ratio Select Start-Up Options (MS_SEL)
1.96 kΩ ± 1% to GND
4.02 kΩ ± 1% to GND
8.06 kΩ ± 1% to GND
16.2 kΩ ± 1% to GND
1.0 kΩ ± 1% to GND
1.96 kΩ ± 1% to VL
4.02 kΩ ± 1% to VL
8.06 kΩ ± 1% to VL
127.0 kΩ ± 1% to GND
1.0 kΩ ± 1% to VL
1.96 kΩ ± 1% to GND
4.02 kΩ ± 1% to GND
1.96 kΩ ± 1% to GND
4.02 kΩ ± 1% to GND
8.06 kΩ ± 1% to GND
16.2 kΩ ± 1% to GND
32.4 kΩ ± 1% to GND
63.4 kΩ ± 1% to GND
127.0 kΩ ± 1% to VL
1.0 kΩ ± 1% to GND
1.0 kΩ ± 1% to GND
1.96 kΩ ± 1% to VL
4.02 kΩ ± 1% to VL
1.96 kΩ ± 1% to VL
4.02 kΩ ± 1% to VL
8.06 kΩ ± 1% to VL
16.2 kΩ ± 1% to VL
32.4 kΩ ± 1% to VL
63.4 kΩ ± 1% to VL
1.0 kΩ ± 1% to VL
1.0 kΩ ± 1% to VL
MS_SEL pin
Table 3. Serial Audio Output Port Start-Up Options (SAOF)
SAOF pin
SAIF pin
Table 2. Serial Audio Input Port Start-Up Options (SAIF)
Master (
Master (
Master (
Master (
Input M/S
Slave
Slave
Slave
Slave
Slave
Output Port Configuration
128 x Fsi
256 x Fsi
384 x Fsi
Left-Justified up to 32-bit data
512
Input Port Configuration
Right-Justified 16-bit data
Right-Justified 20-bit data
Right-Justified 24-bit data
Right-Justified 32-bit data
Right-Justified 16-bit data
Right-Justified 20-bit data
Right-Justified 24-bit data
Right-Justified 32-bit data
Left-Justified 16-bit data
Left-Justified 20-bit data
Left-Justified 24-bit data
Left-Justified 32-bit data
TDM Mode 16-bit data
TDM Mode 20-bit data
TDM Mode 24-bit data
TDM Mode 32-bit data
I²S up to 32-bit data
x Fsi)
I²S 16-bit data
I²S 20-bit data
I²S 24-bit data
I²S 32-bit data
)
)
)
Master (
Master (
Master (
Master (
Output M/S
Slave
Slave
Slave
Slave
Slave
128 x Fso
256 x Fso
384
512
x Fso)
x Fso)
)
)
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CS8421
19