CY7C4225-15AC Cypress Semiconductor Corp, CY7C4225-15AC Datasheet - Page 4

• Manufacturer Part Number: CY7C4225-15AC
• Description: IC SYNC FIFO MEM 1KX18 64LQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C4225-15AC

• Function: Synchronous
• Memory Size: 18K (1K x 18)
• Data Rate: 100MHz
• Access Time: 10ns
• Voltage - Supply: 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Configuration: Dual
• Density: 18Kb
• Access Time (max): 10ns
• Word Size: 18b
• Organization: 1Kx18
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: TQFP
• Clock Freq (max): 66.7MHz
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Supply Current: 45mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1217

Document #: 38-06029 Rev. *C
Pin Definitions
Architecture
The CY7C42X5V consists of an array of 64 to 4K words of 18
bits each (implemented by a dual-port array of SRAM cells), a
read pointer, a write pointer, control signals (RCLK, WCLK,
REN, WEN, RS), and flags (EF, PAE, HF, PAF, FF). The
CY7C42X5V also includes the control signals WXI, RXI, WXO,
RXO for depth expansion.
Resetting the FIFO
Upon power-up, the FIFO must be reset with a Reset (RS)
cycle. This causes the FIFO to enter the Empty condition
signified by EF being LOW. All data outputs go LOW after the
falling edge of RS only if OE is asserted. In order for the FIFO
to reset to its default state, a falling edge must occur on RS
and the user must not read or write while RS is LOW.
FIFO Operation
When the WEN signal is active (LOW), data present on the
D
WCLK signal. Similarly, when the REN signal is active LOW,
data in the FIFO memory will be presented on the Q
outputs. New data will be presented on each rising edge of
RCLK while REN is active LOW and OE is LOW. REN must
set up t
must occur t
An Output Enable (OE) pin is provided to three-state the Q
outputs when OE is deasserted. When OE is enabled (LOW),
data in the output register will be available to the Q
after t
output data on the FIFO that is read enabled.
The FIFO contains overflow circuitry to disallow additional
writes when the FIFO is full, and underflow circuitry to disallow
additional reads when the FIFO is empty. An empty FIFO
maintains the data of the last valid read on its Q
even after additional reads occur.
Note:
RXO
RS
OE
V
1. The same selection sequence applies to reading from the registers. REN is enabled and read is performed on the LOW-to-HIGH transition of RCLK.
Signal Name
0-17
CC
/SMODE
OE
pins is written into the FIFO on each rising edge of the
ENS
. If devices are cascaded, the OE function will only
before RCLK for it to be a valid read function. WEN
ENS
before WCLK for it to be a valid write function.
Read Expansion
Output
Reset
Output Enable
Synchronous
Almost Empty/
Almost Full Flags
Description
(continued)
I/O
O Cascaded – Connected to RXI of next device.
I
I
I
Resets device to empty condition. A reset is required before an initial read or write
operation after power-up.
When OE is LOW, the FIFO’s data outputs drive the bus to which they are
connected. If OE is HIGH, the FIFO’s outputs are in High Z (high-impedance)
state.
Dual-Mode Pin. Asynchronous Almost Empty/Almost Full flags – tied to V
Synchronous Almost Empty/Almost Full flags – tied to V
synchronized to RCLK, Almost Full synchronized to WCLK.)
0−17
0−17
outputs
outputs
0−17
0–17
Programming
The CY7C42X5V devices contain two 12-bit offset registers.
Data present on D
the distance from Empty (Full) that the Almost Empty (Almost
Full) flags become active. If the user elects not to program the
FIFO’s flags, the default offset values are used (see Table 2).
When the Load LD pin is set LOW and WEN is set LOW, data
on the inputs D
the first LOW-to-HIGH transition of the write clock (WCLK).
When the LD pin and WEN are held LOW then data is written
into the Full offset register on the second LOW-to-HIGH
transition of the Write Clock (WCLK). The third transition of the
Write Clock (WCLK) again writes to the Empty offset register
(see Table 1). Writing all offset registers does not have to
occur at one time. One or two offset registers can be written
and then, by bringing the LD pin HIGH, the FIFO is returned to
normal read/write operation. When the LD pin is set LOW, and
WEN is LOW, the next offset register in sequence is written.
The contents of the offset registers can be read on the output
lines when the LD pin is set LOW and REN is set LOW; then,
data can be read on the LOW-to-HIGH transition of the Read
Clock (RCLK).
Table 1. Write Offset Register
LD WEN
0
0
1
1
0
1
0
1
Function
WCLK
0–11
CY7C4225V/4205V/4215V
CY7C4425V/4235V/4245V
0–11
is written into the Empty offset register on
[1]
during a program write will determine
Writing to offset registers:
Empty Offset
Full Offset
No Operation
Write Into FIFO
No Operation
SS
. (Almost Empty
Selection
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CC
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