CY7C4265-10AC Cypress Semiconductor Corp, CY7C4265-10AC Datasheet - Page 12

IC DEEP SYNC FIFO 16KX18 64LQFP

CY7C4265-10AC

Manufacturer Part Number
CY7C4265-10AC
Description
IC DEEP SYNC FIFO 16KX18 64LQFP
Manufacturer
Cypress Semiconductor Corp
Series
CY7Cr
Datasheet

Specifications of CY7C4265-10AC

Function
Synchronous
Memory Size
288K (16K x 18)
Data Rate
100MHz
Access Time
8ns
Voltage - Supply
3.3V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
428-1235
Switching Waveforms
Document #: 38-06004 Rev. *A
Programmable Almost Full Flag Timing (applies only in SMODE (SMODE is LOW))
Write Programmable Registers
Notes:
29. If a write is performed on this rising edge of the write clock, there will be Full
30. PAF offset = m.
31. t
D
WCLK
WCLK
the rising edge of WCLK is less than t
WEN2
0
SKEW3
RCLK
WEN
WEN
REN
–D
PAF
LD
17
is the minimum time between a rising RCLK and a rising WCLK edge for PAF to change state during that clock cycle. If the time between the edge of RCLK and
t
t
CLKH
CLKH
FULL– M + 1 WORDS
(continued)
t
SKEW3
CLK
t
t
ENS
ENS
t
IN FIFO
DS
, then PAF may not change state until the next WCLK rising edge.
PAE OFFSET
t
t
ENS
ENS
t
t
ENH
ENH
t
t
CLKL
CLKL
t
ENH
t
DH
Note
Note
30
PAF OFFSET
29
(m 1) words of the FIFO when PAF goes LOW.
t
PAF
t
ENS
t
SKEW3
FULL– M WORDS
IN FIFO
t
[31]
ENS
PAE OFFSET
D
0
[27]
– D
t
ENH
11
t
PAF synch
CY7C4255
CY7C4265
Page 12 of 22
4255–16
4255–17

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