CY7C4265V-10ASC Cypress Semiconductor Corp, CY7C4265V-10ASC Datasheet - Page 12

IC DEEP SYN FIFO 16KX18 64LQFP

CY7C4265V-10ASC

Manufacturer Part Number
CY7C4265V-10ASC
Description
IC DEEP SYN FIFO 16KX18 64LQFP
Manufacturer
Cypress Semiconductor Corp
Series
CY7Cr
Datasheet

Specifications of CY7C4265V-10ASC

Function
Synchronous
Memory Size
288K (16K x 18)
Data Rate
100MHz
Access Time
8ns
Voltage - Supply
3.3V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
428-1236
Switching Waveforms
Document #: 38-06012 Rev. *A
Programmable Almost Full Flag Timing (applies only in SMODE (SMODE is LOW))
Write Programmable Registers
Notes:
28. If a write is performed on this rising edge of the write clock, there will be Full
29. t
D
WCLK
WCLK
of RCLK and the rising edge of WCLK is less than t
0
SKEW3
RCLK
WEN
WEN
–D
REN
PAF
LD
17
is the minimum time between a rising RCLK and a rising WCLK edge for PAF to change state during that clock cycle. If the time between the edge
t
t
CLKH
CLKH
(continued)
FULL – M + 1 WORDS
t
CLK
t
t
ENS
ENS
t
DS
IN FIFO
PAE OFFSET
t
ENS
t
SKEW3
ENH
t
t
CLKL
CLKL
t
, then PAF may not change state until the next WCLK rising edge.
ENH
t
DH
Note
PAF OFFSET
28
(m 1) words of the FIFO when PAF goes LOW.
t
PAF
t
ENS
t
SKEW3
FULL– M WORDS
IN FIFO
CY7C4255V/CY7C4265V
CY7C4275V/CY7C4285V
t
[29]
ENS
PAE OFFSET
D
0
[26]
– D
t
ENH
11
t
PAF synch
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4275V–19

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