CY7C4265V-10ASC Cypress Semiconductor Corp, CY7C4265V-10ASC Datasheet - Page 16

• Manufacturer Part Number: CY7C4265V-10ASC
• Description: IC DEEP SYN FIFO 16KX18 64LQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C4265V-10ASC

• Function: Synchronous
• Memory Size: 288K (16K x 18)
• Data Rate: 100MHz
• Access Time: 8ns
• Voltage - Supply: 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1236

Table 2. Flag Truth Table
Retransmit
The retransmit feature is beneficial when transferring packets
of data. It enables the receipt of data to be acknowledged by
the receiver and retransmitted if necessary.
The Retransmit (RT) input is active in the stand-alone and
width expansion modes. The retransmit feature is intended for
use when a number of writes equal to or less than the depth
of the FIFO have occurred and at least one word has been
read since the last RS cycle. A HIGH pulse on RT resets the
internal read pointer to the first physical location of the FIFO.
WCLK and RCLK may be free running but must be disabled
during and t
read cycle after retransmit, previously accessed data is read
and the read pointer is incremented until it is equal to the write
pointer. Flags are governed by the relative locations of the
read and write pointers and are updated during a retransmit
Notes:
Document #: 38-06012 Rev. *A
36. n = Empty Offset (Default Values: CY7C4255/65/75/85V n = 127).
37. m = Full Offset (Default Values: CY7C4255/65/75/85V n = 127).
FULL FLAG (FF)
Figure 1. Block Diagram of 8K/16K/32K/64K x 18 Low-Voltage Synchronous FIFO Memory Used in a Width Expansion
0
1 to n
(n+1) to 4096
4097 to (8192–(m+1)) 8193 to (16384
(8192–m)
8192
7C4255V – 8K x 18
DATA IN (D)
PROGRAMMABLE(PAE)
HALF FULL FLAG (HF)
WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
[36]
[37]
RTR
to 8192
after the retransmit pulse. With every valid
LOAD (LD)
36
0
1 to n
(n+1) to 8192
–(m+1))
(16384–m)
16384
16384
7C4265V – 16K x 18 7C4275V – 32K x 18
18
[36]
FF
Number of Words in FIFO
RESET (RS)
[37]
7C4255V
7C4265V
7C4275V
7C4285V
to
WRITE EXPANSION IN (WXI)
READ EXPANSION IN (RXI)
EF
0
1 to n
(n+1) to 16384
16385 to
(32768–(m+1))
(32768–m)
32767
32768
FIRST LOAD (FL)
18
[36]
Configuration
[37]
to
18
cycle. Data written to the FIFO after activation of RT are trans-
mitted also.
The full depth of the FIFO can be repeatedly retransmitted.
Width Expansion Configuration
The CY7C4255/65/75/85V can be expanded in width to pro-
vide word widths greater than 18 in increments of 18. During
width expansion mode all control line inputs are common and
all flags are available. Empty (Full) flags should be created by
ANDing the Empty (Full) flags of every FIFO; the PAE and PAF
flags can be detected from any one device. This technique will
avoid reading data from, or writing data to the FIFO that is
“staggered” by one clock cycle due to the variations in skew
between RCLK and WCLK. Figure 1 demonstrates a 36-word
width by using two CY7C4255/65/75/85Vs.
FF
0
1 to n
(n+1) to 32768
32769 to (65536
–(m+1))
(65536–m)
65535
65536
7C4285V – 64K x 18
RESET (RS)
7C4255V
7C4265V
7C4275V
7C4285V
[36]
[37]
EF
to
CY7C4255V/CY7C4265V
CY7C4275V/CY7C4285V
READ CLOCK (RCLK)
READ ENABLE (REN)
OUTPUT ENABLE (OE)
PROGRAMMABLE (PAF)
18
FF
H
H
H
H
H
DATA OUT (Q)
L
EMPTY FLAG (EF)
PA
H
H
H
H
F
L
L
4275V–24
HF
H
H
H
L
L
L
Page 16 of 20
PA
36
H
H
H
H
E
L
L
EF
H
H
H
H
H
L