CY7C4291-10JC Cypress Semiconductor Corp, CY7C4291-10JC Datasheet - Page 13

• Manufacturer Part Number: CY7C4291-10JC
• Description: IC DEEP SYNC FIFO 128KX9 32-PLCC
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C4291-10JC

• Function: Synchronous
• Memory Size: 1.1M (128K x 9)
• Data Rate: 100MHz
• Access Time: 8ns
• Voltage - Supply: 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-PLCC
• Configuration: Dual
• Density: 1.125Mb
• Access Time (max): 8ns
• Word Size: 9b
• Organization: 128Kx9
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: PLCC
• Clock Freq (max): 100MHz
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Supply Current: 40mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 32
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1244

Document #: 38-06007 Rev. *B
Switching Waveforms
Notes:
23. If a write is performed on this rising edge of the write clock, there will be Full
24. PAF offset = m.
25. 16,384
26. t
Write Programmable Registers
WEN2/LD
Programmable Almost Full Flag Timing
the rising edge of WCLK is less than t
(if applicable)
SKEW2
WEN1
WCLK
D
0
WEN2
–D
WCLK
REN1,
WEN1
RCLK
REN2
is the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to change during that clock cycle. If the time between the rising edge of RCLK and
PAF
8
m words for CY7C4281, 32,768
t
CLKH
t
CLKH
(continued)
FULL
SKEW2
t
CLK
t
t
ENS
ENS
, then PAF may not change state until the next WCLK.
t
DS
(M+1)WORDS
IN FIFO
PAE OFFSET
m words for CY4291.
t
t
ENS
ENS
LSB
t
t
ENH
ENH
t
CLKL
t
CLKL
t
ENH
t
DH
PAE OFFSET
[23]
Note 24
MSB
(m 1) words of the FIFO when PAF goes LOW.
t
PAF
t
ENS
PAF OFFSET
t
SKEW2
(FULL M) WORDS
LSB
IN FIFO
t
ENS
[ 26 ]
[ 25 ]
t
ENH
PAF OFFSET
MSB
t
PAF
CY7C4281
CY7C4291
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