CY7C4241-10AXC Cypress Semiconductor Corp, CY7C4241-10AXC Datasheet - Page 8
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CY7C4241-10AXC
Manufacturer Part Number
CY7C4241-10AXC
Description
IC SYNC FIFO MEM 4KX9 32-TQFP
Manufacturer
Cypress Semiconductor Corp
Series
CY7Cr
Specifications of CY7C4241-10AXC
Function
Synchronous
Memory Size
36K (4K x 9)
Data Rate
100MHz
Access Time
8ns
Voltage - Supply
3.3V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
32-TQFP
Configuration
Dual
Density
32Kb
Access Time (max)
8ns
Word Size
9b
Organization
4Kx9
Sync/async
Synchronous
Expandable
Yes
Bus Direction
Uni-Directional
Clock Freq (max)
100MHz
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Supply Current
35mA
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
32
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY7C4241-10AXC
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Company:
Part Number:
CY7C4241-10AXCT
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Width Expansion Configuration
Word width may be increased by connecting the corresponding
input controls signals of multiple devices. A composite flag
should be created for each of the end-point status flags (EF and
FF). The partial status flags (PAE and PAF) can be detected from
any one device.
using two CY7C42X1s. Any word width can be attained by
adding additional CY7C42X1s.
When the CY7C42X1 is in a Width Expansion Configuration, the
Read Enable (REN2) control input can be grounded (See
Figure
(WEN2/LD) pin is set to LOW at Reset so that the pin operates
as a control to load and read the programmable flag offsets.
Document #: 38-06016 Rev. *D
Figure 3. Block Diagram of 64 x 9, 256 x 9, 512 x 9, 1024 x 9, 2048 x 9, 4096 x 9, 8192 x 9 Synchronous FIFO Memory Used
Write
PROGRAMMABLE (PAF)
Write
DATA IN (D)
Write
3). In this configuration, the Write Enable 2/Load
FULL FLAG (FF) # 1
FULL FLAG (FF) # 2
ENABLE 1 (WEN1)
ENABLE 2/LOAD
CLOCK (WCLK)
Figure 3
(WEN2/LD)
18
demonstrates a 18-bit word width by
9
Read Enable 2 (REN2)
FF
RESET (RS)
CY7C42X1
in a Width Expansion Configuration
EF
9
9
Flag Operation
The CY7C42X1 devices provide four flag pins to indicate the
condition of the FIFO contents. Empty, Full, PAE, and PAF are
synchronous.
Full Flag
The Full Flag (FF) goes LOW when device is full. Write opera-
tions are inhibited whenever FF is LOW regardless of the state
of WEN1 and WEN2/LD. FF is synchronized to WCLK - it is
exclusively updated by each rising edge of WCLK.
Empty Flag
The Empty Flag (EF) goes LOW when the device is empty. Read
operations are inhibited whenever EF is LOW, regardless of the
state of REN1 and REN2. EF is synchronized to RCLK - it is
exclusively updated by each rising edge of RCLK.
Read Enable 2 (REN2)
FF
RESET (RS)
CY7C42X1
EF
CY7C4421/4201/4211/4221
EMPTY FLAG (EF) #1
EMPTY FLAG (EF) #2
Read CLOCK (RCLK)
Read ENABLE 1 (REN1)
OUTPUT ENABLE (OE)
PROGRAMMABLE (PAE)
9
CY7C4231/4241/4251
DATA OUT (Q)
18
Page 8 of 20
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