AD9518-0 Analog Devices, Inc., AD9518-0 Datasheet - Page 53

• Manufacturer Part Number: AD9518-0
• Description: 6-output Clock Generator With Integrated 2.8 Ghz Vco
• Manufacturer: Analog Devices, Inc.

Reg.
Addr
(Hex) Bit(s) Name
1B
1B
1B
1B
<7>
<6>
<5>
<4:0> REFMON Pin Select the signal that is connected to the REFMON pin.
VCO
Frequency
Monitor
REF2
Frequency
Monitor
REF1 (REFIN)
Frequency
Monitor
Control
(
REFIN
)
Description
<5> <4> <3>
1
1
1
1
1
1
1
1
1
1
1
Enable or disable VCO frequency monitor.
<7> = 0; disable VCO frequency monitor.
<7> = 1; enable VCO frequency monitor.
Enable or disable REF2 frequency monitor.
<6> = 0; disable REF2 frequency monitor.
<6> = 1; enable REF2 frequency monitor.
REF1 (REFIN) frequency monitor enable; this is for both REF1 (single-ended) and REFIN (differential) inputs
(as selected by differential reference mode).
<5> = 0; disable REF1 (REFIN) frequency monitor.
<5> = 1; enable REF1 (REFIN) frequency monitor.
<4> <3> <2> <1>
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
<2>
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
<0>
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
<1> <0>
0
1
1
0
0
1
1
0
0
1
1
Level or
Dynamic
Signal
LVL
DYN
DYN
DYN
DYN
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
DYN
DYN
1
0
1
0
1
0
1
0
1
0
1
Rev. 0 | Page 53 of 64
Level or
Dynamic
Signal
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
Signal at REFMON Pin
Ground (dc).
REF1 clock (differential reference when in differential mode).
REF2 clock (N/A in differential mode).
Selected reference to PLL (differential reference when in
differential mode).
Unselected reference to PLL (not available in differential mode).
Status of selected reference (status of differential reference);
active high.
Status of unselected reference (not available in differential mode);
active high.
Status REF1 frequency (active high).
Status REF2 frequency (active high).
(Status REF1 frequency) AND (status REF2 frequency).
(DLD) AND (status of selected reference) AND (status of VCO).
Status of VCO frequency (active high).
Selected reference (low = REF1, high = REF2).
Digital lock detect (DLD); active low.
Holdover active (active high).
LD pin comparator output (active high).
VS (PLL supply).
REF1 clock (differential reference when in differential mode).
REF2 clock (not available in differential mode).
Signal at LD Pin
Status of selected reference (status of differential reference);
active low.
Status of unselected reference (not available in differential
mode); active low.
Status of REF1 frequency (active low).
Status of REF2 frequency (active low).
(Status of REF1 frequency) AND (status of REF2 frequency) .
(DLD) AND (status of selected reference) AND (status of VCO) .
Status of VCO frequency (active low).
Selected reference (low = REF2, high = REF1).
Digital lock detect (DLD); active low.
Holdover active (active low).
N/A—do not use.
AD9518-0