AD9518-0 Analog Devices, Inc., AD9518-0 Datasheet - Page 9

• Manufacturer Part Number: AD9518-0
• Description: 6-output Clock Generator With Integrated 2.8 Ghz Vco
• Manufacturer: Analog Devices, Inc.

CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK CLEANUP USING INTERNAL VCO)
Table 9.
Parameter
LVPECL OUTPUT ABSOLUTE TIME JITTER
CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING EXTERNAL VCXO)
Table 10.
Parameter
LVPECL OUTPUT ABSOLUTE TIME JITTER
CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER NOT USED)
Table 11.
Parameter
LVPECL OUTPUT ADDITIVE TIME JITTER
CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER USED)
Table 12.
Parameter
LVPECL OUTPUT ADDITIVE TIME JITTER
VCO = 2.80 GHz; LVPECL = 155.52 MHz; PLL LBW = 12.8 kHz
VCO = 2.95 GHz; LVPECL = 77.76 MHz; PLL LBW = 12.8 kHz
LVPECL = 245.76 MHz; PLL LBW = 125 Hz
LVPECL = 122.88 MHz; PLL LBW = 125 Hz
LVPECL = 61.44 MHz; PLL LBW = 125 Hz
CLK = 622.08 MHz; LVPECL = 622.08 MHz; Divider = 1
CLK = 622.08 MHz; LVPECL = 155.52 MHz; Divider = 4
CLK = 1.6 GHz; LVPECL = 100 MHz; Divider = 16
CLK = 500 MHz; LVPECL = 100 MHz; Divider = 5
CLK = 2.4 GHz; VCO DIV = 2; LVPECL = 100 MHz;
Divider = 12; Duty-Cycle Correction = Off
Min
Min
Typ
54
77
109
79
114
163
124
176
259
Min
Typ
210
Rev. 0 | Page 9 of 64
Max
Typ
40
80
215
245
Min
Max
Unit
f
f
f
f
f
f
f
f
f
Max
S
S
S
S
S
S
S
S
S
Typ
513
544
rms
rms
rms
rms
rms
rms
rms
rms
rms
Unit
f
S
rms
Unit
f
f
f
f
S
S
S
S
Max
Test Conditions/Comments
Application example based on a typical setup using an
external 245.76 MHz VCXO (Toyocom TCO-2112);
reference = 15.36 MHz; R = 1
Integration BW = 200 kHz to 5 MHz
Integration BW = 200 kHz to 10 MHz
Integration BW = 12 kHz to 20 MHz
Integration BW = 200 kHz to 5 MHz
Integration BW = 200 kHz to 10 MHz
Integration BW = 12 kHz to 20 MHz
Integration BW = 200 kHz to 5 MHz
Integration BW = 200 kHz to 10 MHz
Integration BW = 12 kHz to 20 MHz
rms
rms
rms
rms
Test Conditions/Comments
Distribution section only; does not include PLL and VCO;
uses rising edge of clock signal
Calculated from SNR of ADC method
Unit
f
f
Test Conditions/Comments
Distribution section only; does not include PLL and
VCO; rising edge of clock signal
BW = 12 kHz to 20 MHz
BW = 12 kHz to 20 MHz
Calculated from SNR of ADC method; DCC not used
for even divides
Calculated from SNR of ADC method; DCC on
S
S
rms
rms
Test Conditions/Comments
Application example based on a typical
setup where the reference source is
jittery, so a narrower PLL loop bandwidth
is used; reference = 19.44 MHz; R = 1
Integration BW = 12 kHz to 20 MHz
Integration BW = 12 kHz to 20 MHz
AD9518-0