AD9212BCPZRL7-65 Analog Devices, Inc., AD9212BCPZRL7-65 Datasheet
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AD9212BCPZRL7-65
Manufacturer Part Number
AD9212BCPZRL7-65
Description
Octal, 10-bit, 40/65 Msps Serial Lvds 1.8 V A/d Converter
Manufacturer
Analog Devices, Inc.
Datasheet
1.AD9212BCPZRL7-65.pdf
(56 pages)
FEATURES
Eight ADCs integrated into 1 package
100 mW ADC power per channel at 65 MSPS
SNR = 60.8 dB (to Nyquist)
Excellent linearity
Serial LVDS (ANSI-644, default)
Low power reduced signal option, IEEE 1596.3 similar
Data and frame clock outputs
325 MHz, full power analog bandwidth
2 V p-p input voltage range
1.8 V supply operation
Serial port control
APPLICATIONS
Medical imaging and nondestructive ultrasound
Portable ultrasound and digital beam forming systems
Quadrature radio receivers
Diversity radio receivers
Tape drives
Optical networking
Test equipment
GENERAL DESCRIPTION
The AD9212 is an octal, 10-bit, 40/65 MSPS analog-to-digital
converter (ADC) with an on-chip sample-and-hold circuit that
is designed for low cost, low power, small size, and ease of use.
The product operates at a conversion rate of up to 65 MSPS and
is optimized for outstanding dynamic performance and low
power in applications where a small package size is critical.
The ADC requires a single 1.8 V power supply and LVPECL-/
CMOS-/LVDS-compatible sample rate clock for full performance
operation. No external reference or driver components are
required for many applications.
The ADC automatically multiplies the sample rate clock for
the appropriate LVDS serial data rate. A data clock (DCO)
for capturing data on the output and a frame clock (FCO) for
signaling a new output byte are provided. Individual channel
power-down is supported and typically consumes less than
2 mW when all channels are disabled.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
DNL = ±0.3 LSB (typical)
INL = ±0.4 LSB (typical)
Full-chip and individual-channel power-down modes
Flexible bit orientation
Built-in and custom digital test pattern generation
Programmable clock and data alignment
Programmable output resolution
Standby mode
Serial LVDS 1.8 V A/D Converter
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
The ADC contains several features designed to maximize
flexibility and minimize system cost, such as programmable
clock and data alignment and programmable digital test pattern
generation. The available digital test patterns include built-in
deterministic and pseudorandom patterns, along with custom user-
defined test patterns entered via the serial port interface (SPI®).
The AD9212 is available in a Pb-free, 64-lead LFCSP package. It is
specified over the industrial temperature range of −40°C to +85°C.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
SENSE
VIN+A
VIN+B
VIN+C
VIN+D
VIN+G
VIN–G
VIN+H
VIN–A
VIN–B
VIN–C
VIN–D
VIN+E
VIN–E
VIN+F
VIN–H
VIN–F
REFB
VREF
REFT
Small Footprint. Eight ADCs are contained in a small, space-
saving package; low power of 100 mW/channel at 65 MSPS.
Ease of Use. A data clock output (DCO) operates up to
300 MHz and supports double data rate operation (DDR).
User Flexibility. Serial port interface (SPI) control offers a wide
range of flexible features to meet specific system requirements.
Pin-Compatible Family. This includes the AD9222 (12-bit),
and AD9252 (14-bit).
AVDD
Octal, 10-Bit, 40/65 MSPS
SELECT
RBIAS
REF
AD9212
FUNCTIONAL BLOCK DIAGRAM
AGND
0.5V
CSB
PDWN
©2006 Analog Devices, Inc. All rights reserved.
SERIAL PORT
INTERFACE
SDIO/
Figure 1.
ODM
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
SCLK/
DTP
DRVDD
12
12
12
12
12
12
12
12
CLK+
MULTIPLIER
DATA RATE
SERIAL
SERIAL
SERIAL
SERIAL
SERIAL
SERIAL
SERIAL
SERIAL
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
AD9212
www.analog.com
DRGND
CLK–
DCO+
DCO–
D+A
D–A
D+B
D–B
D+C
D–C
D+D
D–D
D+E
D–E
D+F
D–F
D+G
D–G
D+H
D–H
FCO+
FCO–