AD9212BCPZRL7-65 Analog Devices, Inc., AD9212BCPZRL7-65 Datasheet - Page 22
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AD9212BCPZRL7-65
Manufacturer Part Number
AD9212BCPZRL7-65
Description
Octal, 10-bit, 40/65 Msps Serial Lvds 1.8 V A/d Converter
Manufacturer
Analog Devices, Inc.
Datasheet
1.AD9212BCPZRL7-65.pdf
(56 pages)
AD9212
CLOCK INPUT CONSIDERATIONS
For optimum performance, the AD9212 sample clock inputs
(CLK+ and CLK−) should be clocked with a differential signal.
This signal is typically ac-coupled into the CLK+ and CLK− pins
via a transformer or capacitors. These pins are biased internally
and require no additional bias.
Figure 51 shows one preferred method for clocking the AD9212.
The low jitter clock source is converted from single-ended to
differential using an RF transformer. The back-to-back Schottky
diodes across the secondary transformer limit clock excursions
into the AD9212 to approximately 0.8 V p-p differential. This
helps prevent the large voltage swings of the clock from feeding
through to other portions of the AD9212 and preserves the fast
rise and fall times of the signal, which are critical to low jitter
performance.
If a low jitter clock is available, another option is to ac-couple a
differential PECL signal to the sample clock input pins as shown
in Figure 52. The AD9510/AD9511/AD9512/AD9513/AD9514/
AD9515 family of clock drivers offers excellent jitter performance.
1
CLOCK
1
CLOCK
CLOCK
CLOCK
CLOCK
50
RESISTORS ARE OPTIONAL.
INPUT
50
RESISTORS ARE OPTIONAL.
INPUT
INPUT
INPUT
INPUT
50
50
1
1
Figure 51. Transformer-Coupled Differential Clock
50
0.1µF
Figure 52. Differential PECL Sample Clock
Figure 53. Differential LVDS Sample Clock
50
0.1µF
0.1µF
0.1µF
0.1µF
50
100
1
1
ADT1–1WT, 1:1Z
MINI-CIRCUITS
CLK
CLK
CLK
CLK
LVDS DRIVER
PECL DRIVER
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
XFMR
0.1µF
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
240
0.1µF
0.1µF
SCHOTTKY
HSM2812
DIODES:
240
100
100
0.1µF
0.1µF
0.1µF
0.1µF
CLK+
CLK–
AD9212
CLK+
CLK–
CLK+
CLK–
AD9212
AD9212
ADC
ADC
ADC
Rev. 0 | Page 22 of 56
1
1
In some applications, it is acceptable to drive the sample clock
inputs with a single-ended CMOS signal. In such applications,
CLK+ should be directly driven from a CMOS gate, and the
CLK− pin should be bypassed to ground with a 0.1 μF capacitor
in parallel with a 39 kΩ resistor (see Figure 54). Although the
CLK+ input circuit supply is AVDD (1.8 V), this input is
designed to withstand input voltages up to 3.3 V, making the
selection of the drive logic voltage very flexible.
CLOCK
CLOCK
Clock Duty Cycle Considerations
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals. As a result, these ADCs may
be sensitive to clock duty cycle. Commonly, a 5% tolerance is
required on the clock duty cycle to maintain dynamic performance
characteristics. The AD9212 contains a duty cycle stabilizer (DCS)
that retimes the nonsampling edge, providing an internal clock
signal with a nominal 50% duty cycle. This allows a wide range
of clock input duty cycles without affecting the performance of
the AD9212. When the DCS is on, noise and distortion perfor-
mance are nearly flat for a wide range of duty cycles. However,
some applications may require the DCS function to be off. If so,
keep in mind that the dynamic range performance can be affected
when operated in this mode. See the Memory Map section for
more details on using this feature.
The duty cycle stabilizer uses a delay-locked loop (DLL) to
create the nonsampling edge. As a result, any changes to the
sampling frequency require approximately eight clock cycles
to allow the DLL to acquire and lock to the new rate.
50
RESISTOR IS OPTIONAL.
50
RESISTOR IS OPTIONAL.
INPUT
INPUT
50
50
Figure 54. Single-Ended 1.8 V CMOS Sample Clock
Figure 55. Single-Ended 3.3 V CMOS Sample Clock
0.1µF
0.1µF
1
1
0.1µF
0.1µF
CLK
CLK
CLK
CLK
CMOS DRIVER
CMOS DRIVER
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
0.1µF
OPTIONAL
OPTIONAL
100
100
39k
0.1µF
0.1µF
0.1µF
CLK+
CLK–
CLK+
CLK–
AD9212
AD9212
ADC
ADC