AD9953-PCB Analog Devices, Inc., AD9953-PCB Datasheet
AD9953-PCB
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AD9953-PCB Summary of contents
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... One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.326.8703 Direct Digital Synthesizer AD9953 DAC_R 19 14 IOUT COS(X) DAC IOUT SYSTEM CLOCK 14 SYNC_IN PHASE OFFSET WORD OSK PWRDWNCTL RESET © 2004 Analog Devices, Inc. All rights reserved. AD9953 SET www.analog.com ...
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... Pin Configuration............................................................................. 7 Pin Function Descriptions .............................................................. 8 Typical Performance Characteristics ............................................. 9 Theory of Operation ...................................................................... 12 Component Blocks ..................................................................... 12 Modes of Operation ................................................................... 19 REVISION HISTORY Revision 0: Initial Version Programming AD9953 Features............................................... 22 Serial Port Operation................................................................. 25 Instruction Byte .......................................................................... 27 Serial Interface Port Pin Description....................................... 27 MSB/LSB Transfers .................................................................... 27 Suggested Application Circuits..................................................... 29 Outline Dimensions ....................................................................... 30 ESD Caution................................................................................ 30 Ordering Guide ...
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... DAC to form a digitally programmable, complete high frequency synthesizer capable of generating a frequency-agile analog output sinusoidal waveform 200 MHz. The AD9953 includes an integrated 1024 × 32 static RAM to support flexible frequency sweep capability in several modes. The AD9953 is designed to provide fast frequency hop- ping and fine tuning resolution (32-bit frequency tuning word) ...
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... AD9953 ELECTRICAL SPECIFICATIONS Table 1. Unless otherwise noted, AVDD, DVDD = 1.8 V ± 5%, DVDD_I/O = 3.3 V ± 5%, R Frequency = 20 MHz with REFCLK Multiplier Enabled at 20×. DAC Output Must Be Referenced to AVDD, Not AGND. Parameter REF CLOCK INPUT CHARACTERISTICS Frequency Range REFCLK Multiplier Disabled REFCLK Multiplier Enabled at 4× ...
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... Wake-up time refers to the recovery from analog power-down modes (see the Power-Down Functions of the AD9953 section). The longest time required is for the reference clock multiplier PLL to relock to the reference. The wake-up time assumes there is no capacitor on DACBP and that the recommended PLL loop filter values are used ...
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... AD9953 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Maximum Junction Temperature DVDD_I/O (Pin 43) AVDD, DVDD Digital Input Voltage (DVDD_I/O = 3.3 V) Digital Input Voltage (DVDD_I/O = 1.8 V) Digital Output Current Storage Temperature Operating Temperature Lead Temperature (10 sec Soldering) θ JA θ JC Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device ...
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... DVDD 2 DGND 3 AVDD 4 AGND 5 AVDD 6 AD9953 AGND 7 TOP VIEW (Not to Scale Figure 3. 48-Lead TQFP/EP Rev Page RESET 36 PWRDWNCTL 35 DVDD 34 DGND 33 AGND 32 AGND 31 AGND 30 AVDD 29 AGND 28 AVDD 27 AGND 26 AVDD AD9953 ...
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... DAC. Input Pin Used as an External Power-Down Control (see Table 10 for details). Active High Hardware Reset Pin. Assertion of the RESET pin forces the AD9953 to the initial state, as described in the I/O port register map. Asynchronous Active High Reset of the Serial Port Controller. When high, the current I/O operation is immediately terminated, enabling a new I/O operation to commence once IOSYNC is returned low. If unused, ground this pin ...
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... CENTER 100MHz #RES BW 3kHz VBW 3kHz SWEEP 55.56 s (401 PTS) Figure 160 MHz, FCLK = 400 MSPS, WBSFDR OUT AD9953 MKR1 80.0MHz –61.55dB 1 SPAN 200MHz MKR1 40.0MHz –56.2dB 1 SPAN 200MHz MKR1 0Hz –53.17dB 1R SPAN 200MHz ...
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... AD9953 REF –4dBm ATTEN 10dB 1 0 PEAK LOG –10 10dB/ –20 –30 –40 MARKER 1.105000MHz –5.679dBm –50 – – –80 –90 ST –100 CENTER 1.105MHz #RES BW 30Hz VBW 30Hz Figure 10 1.1 MHz, FCLK = 400 MSPS, NBSFDR, ±1 MHz OUT ...
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... R2 IT 4.0PS/PT 3.1ns Rev Page 9.5 MHz 400 MSPS (Green), OUT CLK 4 ×100 MSPS (Red), and 20 × 20 MSPS (Blue) FALL (R1) = 396.4PS RISE(R2) = 464.3PS REF2 200mV 500ns M 500PS 20.0GS/S IT 10.0PS/PT –100PS A CH1 708mV Figure 19. Comparator Rise and Fall Time at 160 MHz AD9953 ...
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... With the on-chip oscillator enabled, users of the AD9953 connect an external crystal to the REFCLK and REFCLKB inputs to produce a low frequency reference clock in the range of 20 MHz to 30 MHz. The signal generated by the oscillator is buffered before it is delivered to the rest of the chip. This buffered signal is available via the CRYSTAL OUT pin. Bit CFR1< ...
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... The interface allows read/write access to all registers that configure the AD9953. MSB first or LSB first transfer formats are supported. ) The AD9953’s serial interface port can be configured as a single pin SET I/O (SDIO), which allows a 2-wire interface or two unidirectional pins for in/out (SDIO/SDO), which in turn enables a 3-wire inter- face ...
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... AD9953 Table 5. Register Map Register Name (Serial Bit (MSB) Address) Range Bit 7 Digital <7:0> Power- Down Control Load SRR <15:8> Function @ I/O UD Register No.1 Automatic (CFR1) <23:16> Sync (0x00) Enable RAM <31:24> Enable <7:0> 0x00 or 0x01, or 0x02 or 0x03: Bypass Multiplier Control 0x04 to 0x14: 4× to 20× Multiplication Function Register No ...
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... RAM Segment 0 Beginning Address <9:6> RAM Segment 0 Final Address <9:8> RAM Segment 1 Beginning Address <9:6> RAM Segment 1 Final Address <9:8> RAM Segment 2 Beginning Address <9:6> RAM Segment 2 Final Address <9:8> RAM Segment 3 Beginning Address <9:6> RAM Segment 3 Final Address <9:8> AD9953 Default Value OR Profile PS0 = 0 PS1 = 0 PS0 = 0 PS1 = 0 PS0 = 0 ...
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... Control Register Bit Descriptions Control Function Register. No. 1 (CFR1) The CFR1 is used to control the various functions, features, and modes of the AD9953. The functionality of each bit is below. CFR1<31>: RAM Enable Bit CFR1<31> (default). The RAM is powered down to con- serve power. Single-tone mode of operation is active. ...
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... CFR1<0>: Not Used, Leave at 0 Control Function Register No. 2 (CFR2) The CFR2 is used to control the various functions, features, and modes of the AD9953, primarily related to the analog sections of the chip. CFR2<23:12>: Not Used CFR2<11>: High Speed Sync Enable Bit CFR2< ...
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... RAM The AD9953 incorporates a 1024 × 32 block of SRAM. The RAM is a bidirectional single port. Both read and write opera- ° tions from and to the RAM are valid, but they cannot occur simultaneously ...
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... Address 0x04) drives the phase accumulator. When CFR1<31> is Logic 0, the RAM is inactive unless being written to via the serial port. The power-up state of the AD9953 is the single-tone mode, in which the RAM enable bit is inactive. The RAM is segmented into four unique slices controlled by the Profile<1:0> ...
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... Bidirectional ramp mode allows the AD9953 to offer a symmet- rical sweep between two frequencies using the Profile<0> signal as the control input. The AD9953 is programmed for bidirec- tional ramp mode by writing the RAM enable bit true and the RAM mode control bits of RSCW0 to Logic 010(b). In bidirec- tional ramp mode, the Profile< ...
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... The internal profile control capability disen- gages the Profile<1:0> pins and enables the AD9953 to take control of switching between profiles. Modes are defined that allow continuous or single burst profile switches for three combinations of profile selection bits. These are listed in Table 7. When any of the CFR1< ...
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... I/O UPDATE until the appropriate auto-clear control bit is cleared. Shaped On-Off Keying The shaped on-off keying function of the AD9953 allows the user to control the ramp-up and ramp-down time of an on-off emission from the DAC. This function is used in burst trans- missions of digital data to reduce the adverse spectral impact of short, abrupt bursts of data ...
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... TO DAC OSK ENABLE CFR<25> SYNC_CLK LOAD OSK TIMER 0 1 OSK PIN 0 HOLD OUT UP/DN INC/DEC ENABLE RAMP RATE TIMER AUTO SCALE FACTOR GENERATOR Figure 20. On-Off Shaped Keying Block Diagram Rev Page CFR1<26> AMPLITUDE RAMP RATE REGISTER (ASF) LOAD DATA EN CLOCK AD9953 ...
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... The scale factors are synchronized to SYNC_CLK via the I/O UPDATE functionality. Synchronization; Register Updates (I/O UPDATE) Functionality of the SYNC_CLK and I/O UPDATE Data into the AD9953 is synchronous to the SYNC_CLK signal (supplied externally to the user on the SYNC_CLK pin). The I/O UPDATE pin is sampled on the rising edge of the SYNC_CLK. ...
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... With the AD9953, the instruction byte specifies read/write operation and the register address. Serial operations on the AD9953 occur only at the register level, not the byte level. For the AD9953, the serial port controller recognizes the instruction byte register address and automatically generates the proper register byte address ...
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... All data input to the AD9953 is registered on the rising edge of SCLK. All data is driven out of the AD9953 on the falling edge of SCLK. Figure 23 through Figure 26 are useful in understand- ing the general operation of the AD9953 serial port. ...
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... I/O operation is complete. All data written to (read from) the AD9953 must be (will be) in MSB first order. If the LSB mode is active, the serial port controller will generate the least signifi- cant byte address first followed by the next greater significant byte addresses until the I/O operation is complete ...
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... Control PWRDWNCTL = 0 CFR1<3> Don’t Care PWRDWNCTL = 1 CFR1<3> PWRDWNCTL = 1 CFR1<3> drives out of the AD9953 core logic to the analog section and the digital clock generation section of the chip for the external power-down operation. Layout Considerations For the best performance, the following layout guidelines should be observed ...
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... MODULATED/ DEMODULATED SIGNAL REFCLK SAW CRYSTAL REFCLK CRYSTAL OUT REFCLK VCO FREQUENCY TUNING WORD Figure 29. Two AD9953s Synchronized to Provide I and Q Carriers with Independent Phase Offsets for Nulling Rev Page AD9953 PHASE TUNING OFFSET WORD WORD 1 I/I-BAR BASEBAND IOUT LPF AD9953 DDS ...
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... Analog Devices will provide a more ESD-hardy product in the near future at which time this warn- ing will be removed from this data sheet. ORDERING GUIDE Model Temperature Range AD9953YSV –40°C to +105°C AD9953YSV-REEL7 –40°C to +105°C AD9953/PCB 9.00 BSC 7.00 BSC SQ ...
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... NOTES Rev Page AD9953 ...
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... AD9953 NOTES © 2004 Analog Devices, Inc. All rights reserved. Trademarks and regis- tered trademarks are the property of their respective owners. D03357-0-1/04(0) Rev Page ...