AD9953-PCB Analog Devices, Inc., AD9953-PCB Datasheet - Page 26

• Manufacturer Part Number: AD9953-PCB
• Description: 400 Msps 14-bit, 1.8v Cmos Direct Digital Synthesizer
• Manufacturer: Analog Devices, Inc.

AD9953
There are two phases to a communication cycle with the
AD9953. Phase 1 is the instruction cycle, which is the writing of
an instruction byte into the AD9953, coincident with the first
eight SCLK rising edges. The instruction byte provides the
AD9953 serial port controller with information regarding the
data transfer cycle, which is Phase 2 of the communication cycle.
The Phase 1 instruction byte defines whether the upcoming data
transfer is read or write and the serial address of the register
being accessed. (Note that the serial address of the register
being accessed is NOT the same address as the bytes to be
written. See the Example Operation section for details.)
The first eight SCLK rising edges of each communication cycle
are used to write the instruction byte into the AD9953. The
remaining SCLK edges are for Phase 2 of the communication
cycle. Phase 2 is the actual data transfer between the AD9953
SCLK
SCLK
SCLK
SCLK
SDIO
SDIO
SDIO
SDIO
SDO
CS
CS
CS
CS
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INSTRUCTION CYCLE
Figure 26. 2-Wire Serial Port Read Timing—Clock Stall High
INSTRUCTION CYCLE
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INSTRUCTION CYCLE
Figure 24. 3-Wire Serial Port Read Timing—Clock Stall Low
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Figure 25. Serial Port Write Timing—Clock Stall High
Figure 23. Serial Port Write Timing—Clock Stall Low
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and the system controller. The number of bytes transferred
during Phase 2 of the communication cycle is a function of the
register being accessed. For example, when accessing the Control
Function Register No. 2, which is three bytes wide, Phase 2 requires
that three bytes be transferred. If accessing the frequency tuning
word, which is four bytes wide, Phase 2 requires that four bytes
be transferred. After transferring all data bytes per the instruc-
tion, the communication cycle is completed.
At the completion of any communication cycle, the AD9953
serial port controller expects the next eight rising SCLK edges
to be the instruction byte of the next communication cycle. All
data input to the AD9953 is registered on the rising edge of
SCLK. All data is driven out of the AD9953 on the falling edge
of SCLK. Figure 23 through Figure 26 are useful in understand-
ing the general operation of the AD9953 serial port.
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DATA TRANSFER CYCLE
DATA TRANSFER CYCLE
DATA TRANSFER CYCLE
DATA TRANSFER CYCLE
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DON'T CARE
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