AD9775-EB Analog Devices, Inc., AD9775-EB Datasheet - Page 45

AD9775-EB

Manufacturer Part Number

AD9775-EB

Description

14-bit, 160 Msps, 2?/4?/8? Interpolating Dual Txdac+ Digital-to-analog Converter

Manufacturer

Analog Devices, Inc.

Datasheet

1.AD9775-EB.pdf (56 pages)

Current page: 45 of 56
Download datasheet (2Mb)

Figure 102. Test Configuration for AD9775 in One-Port Mode with PLL Enabled, Signal Generator Frequency = One-Half Interleaved Input Data Rate,

Figure 101. Test Configuration for AD9775 in Two-Port Mode with PLL Enabled, Signal Generator Frequency = Input Data Rate,

ONEPORTCLK = Interleaved Input Data Rate, DAC Output Data Rate = Signal Generator Frequency × Interpolation Rate

NOTES

1. TO USE PECL CLOCK DRIVER, SOLDER JP41 AND JP42 AND REMOVE TRANSFORMER T1.

2. IN TWO-PORT MODE, IF DATACLK/PLL_LOCK IS PROGRAMMED TO OUTPUT PIN 8, JP25

NOTES

1. TO USE PECL CLOCK DRIVER, SOLDER JP41 AND JP42 AND REMOVE TRANSFORMER T1.

AND JP39 SHOULD BE SOLDERED. IF DATACLK/PLL_LOCK IS PROGRAMMED TO OUTPUT

PIN 53, JP46 AND JP47 SHOULD BE SOLDERED. SEE THE TWO-PORT DATA INPUT MODE

FOR MORE INFORMATION.

DAC Output Data Rate = Signal Generator Frequency × Interpolation Rate

INPUT CLOCK

JUMPER CONFIGURATION FOR TWO-PORT MODE PLL ON

JP12 –

JP24 –

JP25 –

JP26 –

JP27 –

JP31 –

JP32 –

JP33 –

JUMPER CONFIGURATION FOR ONE-PORT MODE PLL ON

JP12 –

JP24 –

JP25 –

JP26 –

JP27 –

JP31 –

JP32 –

JP33 –

AWG2021

JP1 –

JP2 –

JP3 –

JP5 –

JP6 –

AWG2021

JP1 –

JP2 –

JP3 –

JP5 –

JP6 –

DG2020

SOLDERED/IN

LECROY

PULSE

GENERATOR

LECROY

PULSE

GENERATOR

40-PIN RIBBON CABLE

UNSOLDERED/OUT

Rev. E | Page 45 of 56

TRIG

INP

DAC1, DB13–DB0

DAC2, DB13–DB0

DAC1, DB13–DB0

DAC2, DB13–DB0

ONEPORTCLK

DATACLK

SIGNAL GENERATOR

CLK+/CLK–

AD9775

AD9775-EB Analog Devices, Inc., AD9775-EB Datasheet - Page 45

AD9775-EB

Related parts for AD9775-EB