AD9775-EB Analog Devices, Inc., AD9775-EB Datasheet - Page 46

AD9775-EB

Manufacturer Part Number

AD9775-EB

Description

14-bit, 160 Msps, 2?/4?/8? Interpolating Dual Txdac+ Digital-to-analog Converter

Manufacturer

Analog Devices, Inc.

Datasheet

1.AD9775-EB.pdf (56 pages)

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AD9775

Figure 103. Test Configuration for AD9775 in Two-Port Mode with PLL Disabled, DAC Output Data Rate = Signal Generator Frequency,

Figure 104. Test Configuration for AD9775 in One-Port Mode with PLL Disabled, DAC Output Data Rate = Signal Generator Frequency,

ONEPORTCLK = Interleaved Input Data Rate = 2× Signal Generator Frequency/Interpolation Rate

NOTES

1. TO USE PECL CLOCK DRIVER, SOLDER JP41 AND JP42 AND REMOVE TRANSFORMER T1.

2. IN TWO-PORT MODE, IF DATACLK/PLL_LOCK IS PROGRAMMED TO OUTPUT PIN 8, JP25

NOTES

1. TO USE PECL CLOCK DRIVER, SOLDER JP41 AND JP42 AND REMOVE TRANSFORMER T1.

AND JP39 SHOULD BE SOLDERED. IF DATACLK/PLL_LOCK IS PROGRAMMED TO OUTPUT

PIN 53, JP46 AND JP47 SHOULD BE SOLDERED. SEE THE TWO-PORT DATA INPUT MODE

FOR MORE INFORMATION.

INPUT CLOCK

JUMPER CONFIGURATION FOR TWO-PORT MODE PLL OFF

JUMPER CONFIGURATION FOR ONE-PORT MODE PLL OFF

JP12 –

JP24 –

JP25 –

JP26 –

JP27 –

JP31 –

JP32 –

JP33 –

JP12 –

JP24 –

JP25 –

JP26 –

JP27 –

JP31 –

JP32 –

JP33 –

AWG2021

JP1 –

JP2 –

JP3 –

JP5 –

JP6 –

AWG2021

JP1 –

JP2 –

JP3 –

JP5 –

JP6 –

DG2020

DATACLK = Signal Generator Frequency/Interpolation Rate

SOLDERED/IN

LECROY

PULSE

GENERATOR

LECROY

PULSE

GENERATOR

40-PIN RIBBON CABLE

UNSOLDERED/OUT

Rev. E | Page 46 of 56

TRIG

INP

ONEPORTCLK

DAC1, DB13–DB0

DAC2, DB13–DB0

DAC1, DB13–DB0

DAC2, DB13–DB0

DATACLK

SIGNAL GENERATOR

CLK+/CLK–

AD9775

AD9775-EB Analog Devices, Inc., AD9775-EB Datasheet - Page 46

AD9775-EB

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