AD9219BCPZRL-65 Analog Devices, Inc., AD9219BCPZRL-65 Datasheet - Page 22

• Manufacturer Part Number: AD9219BCPZRL-65
• Description: Quad, 10-bit, 40/65 Msps Serial Lvds 1.8 V A/d Converter
• Manufacturer: Analog Devices, Inc.

AD9219
Clock Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality of the
clock input. The degradation in SNR at a given input frequency
(f
In this equation, the rms aperture jitter represents the root mean
square of all jitter sources, including the clock input, analog input
signal, and ADC aperture jitter specifications. IF undersampling
applications are particularly sensitive to jitter (see Figure 55).
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the AD9219.
Power supplies for clock drivers should be separated from the
ADC output driver supplies to avoid modulating the clock signal
with digital noise. Low jitter, crystal-controlled oscillators make
the best clock sources. If the clock is generated from another
type of source (by gating, dividing, or other methods), it should
be retimed by the original clock at the last step.
Refer to the
Application Note
performance as it relates to ADCs (visit www.analog.com).
A
) due only to aperture jitter (t
SNR degradation = 20 × log 10 [1/2 × π × f
130
120
110
100
90
80
70
60
50
40
30
1
10 BITS
RMS CLOCK JITTER REQUIREMENT
Figure 55. Ideal SNR vs. Input Frequency and Jitter
AN-501 Application Note
for more in-depth information about jitter
ANALOG INPUT FREQUENCY (MHz)
10
0.125 ps
0.25 ps
J
0.5 ps
1.0 ps
2.0 ps
) can be calculated by
and the
100
AN-756
A
× t
16 BITS
14 BITS
12 BITS
J
]
1000
Rev. 0 | Page 22 of 52
Power Dissipation and Power-Down Mode
As shown in Figure 56 and Figure 57, the power dissipated by
the AD9219 is proportional to its sample rate. The digital power
dissipation does not vary much because it is determined primarily
by the DRVDD supply and bias current of the LVDS output drivers.
Figure 56. Supply Current vs. f
Figure 57. Supply Current vs. f
200
180
160
140
120
100
140
120
100
80
60
40
20
80
60
40
20
0
0
10
10
15
20
20
30
DRVDD CURRENT
ENCODE (MSPS)
AVDD CURRENT
ENCODE (MSPS)
DRVDD CURRENT
TOTAL POWER
AVDD CURRENT
TOTAL POWER
SAMPLE
SAMPLE
25
for f
for f
40
IN
IN
= 10.3 MHz, f
= 10.3 MHz, f
30
50
35
SAMPLE
SAMPLE
60
= 40 MSPS
= 65 MSPS
40
390
370
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250
360
340
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200
180