AD9219BCPZRL-65 Analog Devices, Inc., AD9219BCPZRL-65 Datasheet - Page 30

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AD9219BCPZRL-65

Manufacturer Part Number
AD9219BCPZRL-65
Description
Quad, 10-bit, 40/65 Msps Serial Lvds 1.8 V A/d Converter
Manufacturer
Analog Devices, Inc.
Datasheet
AD9219
SCLK
Table 14. Serial Timing Definitions
Parameter
t
t
t
t
t
t
t
SDIO
DS
DH
CLK
S
H
HI
LO
CSB
DON’T CARE
DON’T CARE
t
S
R/W
Timing (minimum, ns)
5
2
40
5
2
16
16
t
DS
W1
W0
t
DH
A12
A11
t
HI
Description
Set-up time between the data and the rising edge of SCLK
Hold time between the data and the rising edge of SCLK
Period of the clock
Set-up time between CSB and SCLK
Hold time between CSB and SCLK
Minimum period that SCLK should be in a logic high state
Minimum period that SCLK should be in a logic low state
A10
t
Figure 68. Serial Timing Details
LO
A9
Rev. 0 | Page 30 of 52
t
CLK
A8
A7
D5
D4
D3
D2
D1
D0
t
H
DON’T CARE
DON’T CARE

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