74LVC1G74DC,125 NXP Semiconductors, 74LVC1G74DC,125 Datasheet - Page 12

• Manufacturer Part Number: 74LVC1G74DC,125
• Description: IC SNGL D FF POS-EDG TRIG 8VSSOP
• Manufacturer: NXP Semiconductors
• Series: 74LVCr
• Type: D-Typer

Specifications of 74LVC1G74DC,125

• Output Type: Differential
• Package / Case: US8, 8-VSSOP
• Function: Set(Preset) and Reset
• Number Of Elements: 1
• Number Of Bits Per Element: 1
• Frequency - Clock: 200MHz
• Trigger Type: Positive Edge
• Current - Output High, Low: 32mA, 32mA
• Voltage - Supply: 1.65 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Number Of Circuits: 1
• Logic Family: 74LVC
• Logic Type: CMOS
• Polarity: Inverting/Non-Inverting
• Input Type: Single-Ended
• Propagation Delay Time: 13.4 ns
• High Level Output Current: - 32 mA
• Low Level Output Current: 32 mA
• Supply Voltage (max): 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Supply Voltage (min): 1.65 V
• Technology: CMOS
• Number Of Bits: 1
• Number Of Elements: 1
• Clock-edge Trigger Type: Positive-Edge
• Operating Supply Voltage (typ): 1.8/2.5/3.3/5V
• Package Type: VSSOP
• Operating Supply Voltage (min): 1.65V
• Operating Supply Voltage (max): 5.5V
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Delay Time - Propagation: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4494-2; 74LVC1G74DC-G; 74LVC1G74DC-G; 935274973125

NXP Semiconductors
74LVC1G74
Product data sheet
Fig 9.
Measurement points are given in
V
The set (SD) and reset (RD) input to output (Q, Q) propagation delays, the set and reset pulse widths and
the RD to CP recovery time
OL
and V
OH
are typical output voltage levels that occur with the output load.
CP input
SD input
RD input
Q output
Q output
GND
GND
GND
V
V
V
V
OH
OH
OL
OL
Table
V
V
V
I
I
I
All information provided in this document is subject to legal disclaimers.
10.
V
M
Single D-type flip-flop with set and reset; positive edge trigger
Rev. 9 — 5 August 2010
t
V
V
W
M
M
t
t
PLH
PHL
V
M
t
W
t
t
PHL
PLH
V
M
mnb142
t
t
rec
rec
74LVC1G74
© NXP B.V. 2010. All rights reserved.
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