74LVC1G74GT,115 NXP Semiconductors, 74LVC1G74GT,115 Datasheet - Page 11

• Manufacturer Part Number: 74LVC1G74GT,115
• Description: IC D-TYPE F-F POS-EDG-TRG 8XSON
• Manufacturer: NXP Semiconductors
• Series: 74LVCr
• Type: D-Typer

Specifications of 74LVC1G74GT,115

• Output Type: Differential
• Package / Case: 8-XSON
• Function: Set(Preset) and Reset
• Number Of Elements: 1
• Number Of Bits Per Element: 1
• Frequency - Clock: 200MHz
• Trigger Type: Positive Edge
• Current - Output High, Low: 32mA, 32mA
• Voltage - Supply: 1.65 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Number Of Circuits: 1
• Logic Family: 74LVC
• Logic Type: D-Type Flip-Flop
• Polarity: Inverting/Non-Inverting
• Input Type: Single-Ended
• Propagation Delay Time: 4.1 ns
• High Level Output Current: - 32 mA
• Low Level Output Current: 32 mA
• Supply Voltage (max): 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Supply Voltage (min): 1.65 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Delay Time - Propagation: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-3255-2; 74LVC1G74GT-G; 935278917115

NXP Semiconductors
12. Waveforms
Table 10.
74LVC1G74
Product data sheet
Supply voltage
V
1.65 V to 1.95 V
2.3 V to 2.7 V
2.7 V
3.0 V to 3.6 V
4.5 V to 5.5 V
Fig 8.
CC
Measurement points are given in
The shaded areas indicate when the input is permitted to change for predictable output performance.
V
The clock input (CP) to output (Q, Q) propagation delays, the clock pulse width, the D to CP set-up, the
CP to D hold times and the maximum frequency
OL
Measurement points
and V
OH
are typical output voltage levels that occur with the output load.
CP input
Q output
Q output
D input
GND
GND
V
V
V
V
Table
OH
OH
OL
OL
V
V
Input
V
0.5 × V
0.5 × V
1.5 V
1.5 V
0.5 × V
All information provided in this document is subject to legal disclaimers.
I
I
M
10.
V
M
t
PLH
CC
CC
CC
t
Single D-type flip-flop with set and reset; positive edge trigger
su
Rev. 9 — 5 August 2010
t
V
h
M
V
V
M
M
t
PHL
1/f
max
t
W
t
PHL
t
su
t
h
Output
V
0.5 × V
0.5 × V
1.5 V
1.5 V
0.5 × V
M
mnb141
t
PLH
CC
CC
CC
74LVC1G74
© NXP B.V. 2010. All rights reserved.
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