74HC377D,652 NXP Semiconductors, 74HC377D,652 Datasheet - Page 7

• Manufacturer Part Number: 74HC377D,652
• Description: IC OCTAL D F-F POS-EDGE 20-SOIC
• Manufacturer: NXP Semiconductors
• Series: 74HCr
• Type: D-Type Busr

Specifications of 74HC377D,652

• Output Type: Non-Inverted
• Package / Case: 20-SOIC (7.5mm Width)
• Function: Standard
• Number Of Elements: 1
• Number Of Bits Per Element: 8
• Frequency - Clock: 83MHz
• Delay Time - Propagation: 13ns
• Trigger Type: Positive Edge
• Voltage - Supply: 2 V ~ 6 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Number Of Circuits: 1
• Logic Family: HC
• Logic Type: D-Type Edge Triggered Flip-Flop
• Polarity: Non-Inverting
• Input Type: Single-Ended
• Propagation Delay Time: 13 ns at 5 V
• High Level Output Current: - 5.2 mA
• Low Level Output Current: 5.2 mA
• Supply Voltage (max): 6 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Supply Voltage (min): 2 V
• Technology: CMOS
• Number Of Bits: 8
• Number Of Elements: 1
• Clock-edge Trigger Type: Positive-Edge
• Operating Supply Voltage (typ): 5V
• Package Type: SOIC W
• Frequency (max): 24MHz
• Operating Supply Voltage (min): 2V
• Operating Supply Voltage (max): 6V
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 20
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Output High, Low: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 568-2670-5; 933713980652

Philips Semiconductors
AC WAVEFORMS
PACKAGE OUTLINES
See
December 1990
Octal D-type flip-flop with data enable;
positive-edge trigger
(1) HC : V
Fig.6
The shaded areas indicate when the input is permitted to
change for predictable output performance.
(1) HC : V
Fig.7
“74HC/HCT/HCU/HCMOS Logic Package Outlines”
HCT : V
HCT : V
Waveforms showing the clock (CP) to output (Q
transition times and the maximum clock pulse frequency.
Waveforms showing the data set-up and hold times from the data input (D
(E) to the clock (CP).
M
M
M
M
= 50%; V
= 1.3 V; V
= 50%; V
= 1.3 V; V
I
I
I
I
= GND to V
= GND to V
= GND to 3 V.
= GND to 3 V.
CC
CC
.
.
.
n
7
) propagation delays, the clock pulse width, output
n
) and from the data enable input
74HC/HCT377
Product specification