BUS-61566-xxxx Data Device, BUS-61566-xxxx Datasheet

BUS-61566-xxxx

Manufacturer Part Number

BUS-61566-xxxx

Description

Advanced Integrated MUX Hybrid

Manufacturer

Data Device

Datasheet

1.BUS-61566-XXXX.pdf (4 pages)

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DESCRIPTION

DDC’s

Integrated Mux (AIM) Hybrid is a

complete

Controller (BC), Remote Terminal

Unit (RTU), and Bus Monitor (MT)

device. Packaged in a single 78-pin

DIP package, the BUS-61553 con-

tains dual low-power transceivers,

complete BC/RT/MT protocol logic, a

MIL-STD-1553-to-host interface unit

and 8K x 16 RAM.

Using an industry standard dual

transceiver and standard status and

control signals, the BUS-61553 sim-

plifies system integration at both the

MIL-STD-1553 and host processor

interface levels.

All 1553 operations are controlled

through the CPU access to the

BUS A

BUS B

DATA

TRANSFORMER A

TRANSFORMER B

BUS-25679

BUS-61553

BUS-25679

MIL-STD-1553

Advanced

TRANSCEIVER A

TRANSCEIVER B

Bus

TIME OUT

MIL-STD-1553 ADVANCED INTEGRATED

768 s

INH

shared 8K x 16 RAM. To ensure

maximum design flexibility, memory

control lines are provided for attach-

ing external RAM to the BUS-61553

address and data buses and for dis-

abling internal memory; the total

combined memory space can be

expanded to 64K x 16. All 1553 trans-

fers are entirely memory-mapped;

thus the CPU interface requires

minimal hardware and/or software

support.

The BUS-61553 operates over the

full military -55°C to +125°C temper-

ature range. Available screened to

MIL-PRF-38534, the BUS-61553 is

ideal for demanding military and

industrial

interface applications.

FIGURE 1. BU-61553 BLOCK DIAGRAM

CHANNEL A

CHANNEL B

ENCODER/

DECODER

ENCODER/

DECODER

microprocessor-to-1553

CONTROLLER

SHARED RAM

PROTOCOL

MEMORY

TIMING

8K x 16

RAM

CONTENTION

RESOLVER

CHECKER

PARITY

• Fully Intergrated Terminal

• CMOS and Bipolar Technologies

• Internal Interrupt Status and Time

• High Reliability

• 883B Processing Available

MUX ( AIM ) HYBRID

Including:

–Dual Transceiver

–BC/RT/MT Protocol

–Memory Management Unit

–Processor lnterface Logic

–8K x 16 RAM

Tag Registers

RT ADDR

GENERATOR

TIMING

INTERRUPT

CPU

D15-D00

A15-A00

FEATURES

BUS-61553

STRBD

READYD

RD/WR

MEM/REG

EXTEN

EXTLD

INT

CLOCK IN

MSTRCLR

SELECT

RTAD0

RTAD1

RTAD2

RTAD3

RTAD4

RTAD P

RTPARERR

Related parts for BUS-61566-xxxx

BUS-61566-xxxx Summary of contents

Page 1

... RAM. To ensure maximum design flexibility, memory control lines are provided for attach- ing external RAM to the BUS-61553 address and data buses and for dis- abling internal memory; the total combined memory space can be expanded to 64K x 16. All 1553 trans- fers are entirely memory-mapped ...

Page 2

... Variables Test Data 5 = -40°C to +85°C with Variables Test Data 8 = 0°C to +70°C with Variables Test Data Power Supply 3 = -15 V Transceivers 4 = -12 V Transceivers Transceivers–Call Factory 6 = Transceivers–Use with BUS-63102II–Call Factory Packaging 5 = DDIP 6 = Flat Pack 2 ...

Page 3

NOTES 3 ...

Page 4

... The information in this data sheet is believed to be accurate; however, no responsibility is assumed by Data Device Corporation for its use, and no license or rights are L - DSN granted by implication or otherwise in connection therewith. Specifications are subject to change without notice. 105 Wilbur Place, Bohemia, New York 11716-2482 For Technical Support - 1-800-DDC-5757 ext. 7257 or 7381 Headquarters - Tel: (631) 567-5600 ext ...

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